Digital Electronics  (ELEC 3500)

Instructor

        Ralph Mason                                                                                                                                                                                                    
        Office Hours (ME5148) :   Tuesday/Thursday 10:00-11:00 a.m.                                                                                                                                             

Course Objective

        This the first undergraduate course on Digital Electronics, better known today's as VLSI (Very Large
        Scale Integrated Circuits.) The course introduces the concepts of CMOS logic gates design, designing
        digital modules using Verilog HDL (Hardware Description Language), and system clocking and timing
        issues.

Course Outline

          Logic Gates              Abstraction Levels, MOS Transistor, CMOS Digital Gates, Logic Styles
          Design with HDL       Verilog Structure, Modules, Variables, Timing, Procedures, ASICs and FPGAs
          Circuit Timing             Clocking, Hazards, Races, Metastability, Asynchronous Techniques, Verification

References

           Jan Rabaey, Digital Integrated Circuits, Prentice Hall, 1996
           S. Palnitkar, Verilog HDL, Prentice Hall, 1996
           J. P. Hayes, Introduction to Digital Logic Design, Addison Wesley, 1993

Marking Scheme

            Laboratory                          20%             In ME-4166
            Assignments                        10%
            Midterm Exam                    20%            In class on Thursday, October 23.
            Final Exam                          50%            Final Exam paper is for evaluation only 
                                                                          and will not be returned to students.
                                                                          Students have to pass the final exam to pass the course
            Bonus Questions                 5%

Teaching Assistants

 

Labs

          Lab reports are due 4:40 p.m. on the day following the lab session you are attending.
          Sometimes the required report is just answers to the questions asked in the lab description.
          Submit one report per group of two partners. Each lab report must clearly indicate the
          names and ID numbers of the partners, the date the lab was done, and lab's topic or number.
          Lab reports must be placed in the lab boxes before 4:40 pm of the due date. There is a 25% penalty
          for lab reports up to one week late, 50% for two weeks late, 75% for three weeks late, and
          100% for four weeks late. All labs must be completed to pass the course. Labs are held in ME-4166

Time Table

 

 

• Verilog Tutorial 
• Icarus Verilog