Digital Electronics  (ELEC 3500)


        Ralph Mason                                                                                                                                                                                                    
        Office Hours (ME5148) :   Tuesday/Thursday 10:00-11:00 a.m.                                                                                                                                             

Course Objective

        This the first undergraduate course on Digital Electronics, better known today's as VLSI (Very Large
        Scale Integrated Circuits.) The course introduces the concepts of CMOS logic gates design, designing
        digital modules using Verilog HDL (Hardware Description Language), and system clocking and timing

Course Outline

          Logic Gates              Abstraction Levels, MOS Transistor, CMOS Digital Gates, Logic Styles
          Design with HDL       Verilog Structure, Modules, Variables, Timing, Procedures, ASICs and FPGAs
          Circuit Timing             Clocking, Hazards, Races, Metastability, Asynchronous Techniques, Verification


           Jan Rabaey, Digital Integrated Circuits, Prentice Hall, 1996
           S. Palnitkar, Verilog HDL, Prentice Hall, 1996
           J. P. Hayes, Introduction to Digital Logic Design, Addison Wesley, 1993

Marking Scheme

            Laboratory                          20%             In ME-4166
            Assignments                        10%
            Midterm Exam                    20%            In class on Thursday, October 23.
            Final Exam                          50%            Final Exam paper is for evaluation only 
                                                                          and will not be returned to students.
                                                                          Students have to pass the final exam to pass the course
            Bonus Questions                 5%

Teaching Assistants

         Name               Email/Office Hours
Zhanjun (JJ) Bai             ME5138  Tues. 12 - 1 p.m.  
Owen Marsh   AP322 Monday 12 - 1 p.m.
Abdulhak (Abdul) Nagy         ME5128  Tues. 1:30 - 2:30 p.m. 
Xing Zhou             ME5137  Wed. 10 - 11 a.m.


                          For Lab Instruction go to culearn course web page          

          Lab reports are due 4:40 p.m. on the day following the lab session you are attending.
          Sometimes the required report is just answers to the questions asked in the lab description.
          Submit one report per group of two partners. Each lab report must clearly indicate the
          names and ID numbers of the partners, the date the lab was done, and lab's topic or number.
          Lab reports must be placed in the lab boxes before 4:40 pm of the due date. There is a 25% penalty
          for lab reports up to one week late, 50% for two weeks late, 75% for three weeks late, and
          100% for four weeks late. All labs must be completed to pass the course. Labs are held in ME-4166

Time Table


Last Update: 08 September 2014, 11:00 a.m.

Contrary to what I said in class labs will start next week on Monday September 8th.

The first lab is intro lab so there is no prelab




Dates in 2014




 0,1  Sep 4-12  Introduction &  MOSFET

 2  Sep 15-19  CMOS Logic Gates

Also some discussion on Asynchronous Circuits
in preperation for labs
 3  Sep 22-26  CMOS Logic Gates and
 Intro to Verilog HDL

- Assignment 1 , due Oct 7, 2014, in class
- Old Assignment 1
- Old Assignmet 1 Solution

 4  Sep 29-Oct 3  Verilog HDL I

- Introduction to Verilog
- Example verilog code

 5  Oct 6-10   Verilog HDL II
 Sequential Circuits

- Assignment 2 , due Oct 21 , 2014, in class  
Old Assignment 2
- Old Assignment 2 Solution

 Oct 13-17
 Digital Circuit Implementation 
 7  Oct 20-24   Asynchronous

 Midterm on Thursday Oct. 23rd in class

- Midterm Exam 2012
- Midterm Exam 2010
- Midterm Exam 2005 with Solution
- Midterm Exam 2004
- Solution to Midterm Exam 2004
- Winter 2002 Midterm with Solution
- 2001Midterm with Solution
- sample problems I
- sample problems II

 8  Oct 27-31      Fall Break No Classes or Labs
 9  Nov 3-7  System Clocking  

 10  Nov 10-14  
  System Clocking  & Hazards
- Assignment 3 , due November 28, 2014 in class
- Old Assignment 3  
- Old Assignment 3 Solution
 11  Nov 17-21   Hazards
 Nov 24-28

Digital Design Verification & Memory and Signal Technologies

 Dec 1-5   Review  

A Final Exam Sample
Final Exam Solution

Final Exam 2008
Final Exam 2011
-sample problems III


- Other Section Assignment 2 with Solution
- Other Section Assignment 3 with Solution
- Other Section Assignment 4 with Solution
- Other Section Midterm with Solution


Academic Accommodation

You may need special arrangements to meet your academic obligations during the term. For an accommodation request the processes are as follows:

Pregnancy obligation: write to me with any requests for academic accommodation during the first two weeks of class, or as soon as possible after the need for accommodation is known to exist. For more details visit the Equity Services website:

Religious obligation: write to me with any requests for academic accommodation during the first two weeks of class, or as soon as possible after the need for accommodation is known to exist. For more details visit the Equity Services website:

Students with disabilities requiring academic accommodations: in this course must register with the Paul Menton Centre for Students with Disabilities (PMC) for a formal evaluation of disability-related needs. Documented disabilities could include but are not limited to mobility/physical impairments, specific Learning Disabilities (LD), psychiatric/psychological disabilities, sensory disabilities, Attention Deficit Hyperactivity Disorder (ADHD), and chronic medical conditions. Registered PMC students are required to contact the PMC, 613-520-6608, every term to ensure that I receive your Letter of Accommodation, no later than two weeks before the first assignment is due or the first in-class test/midterm requiring accommodations. If you only require accommodations for your formally scheduled exam(s) in this course, please submit your request for accommodations to PMC by the last official day to withdraw from classes in each term. For more details visit the PMC website:

Health and Safety

All students and TAs are required to read the University Health-And-Safety document .
The parts that seems to especially apply to ELEC 3500 are:
Sect 5 part a)  Neither food nor beverages are permitted in the lab.
Sect 5 part i)  Know:
    Where the nearest fire extinguisher is.
  The number for emergencies. It is 613-520-4444 or just 4444 on Carleton phones,
    Where a first aid kit is. There is one in 4257 ME beside the single door. However do not treat things yourself; go to
            HEALTH AND COUNSELLING SERVICES (building TT on the Campus Map)
            2600 Training and Technology Centre, 613-520-6674.
Sect 6.3 part a) Clean up!

Ralph Mason's Home Page
This page last updated on Sept 8, 2014.
Copyright  2014 Ralph Mason.