Title Page
All RTL Code
Simplified Hardware Diagrams for each module.
- Registers must be shown as boxes with a clock input, combinational logic as 'clouds'
- For each always block or assign statement you need to draw a seperate 'cloud' or register.
- The inputs/outputs to a 'cloud' or register must be labelled
- State Diagrams must be shown in the 'combinational logic cloud' that controls 'nextstate'
- Output definitions are normally shown in another 'combinational logic cloud' with a description of when
the output is true. (eg. leds_on = (state==PLAY) )
Top Level Testbench
- Must include a win, favour the loser, jump the light
- Must simulate reaction time of the player
- Must be self checking
Top Level Simulation Log File from Modelsim on Gate-Level. Proves Self-Check works!
Top Level Waveform for RTL with your NAME ANNOTATED ON IT showing at least the following signals:
- pbl, pbr, leds, score, slowen, rout, mc_state, winrnd, led_control
- NOTE: Comment waveform extensively to describe the important cases
Top Level Waveform for Gate-Level with your NAME ANNOTATED ON IT Showing at least the following signals:
- pbl, pbr, leds, + some miscillaneous internal gate-level signals
Screenshot of FPGA Express showing proper synthesis of entire project
Conclusions - what would you do differently?