ELEC3500                  Sample Problems

 

Short Answer

 

1.     If CMOS circuits are built with NAND and NOR gates, why do we design the circuits using AND and OR gates?

 

It is easier to understand the functionality of a circuit without the multiple inversions you get with NAND and NORgates.

 

2.     What do we know about a logic circuit that has two inverting circles back to back (i.e. directly connected to each other).

 

They cancel each other out and can be removed.

 

3.     DeMorgan's THm. Allows us to convert an AND gate into what type of gate?

 

A NOR gate with inverted inputs.

 

4.     Generally, how do we convert from AND/OR to NAND/NOR circuits?

 

Insert back to back inverting circles between gates (i.e. cancel each other out and have no effect on overall logic).  Starting at the outputs and going towards the inputs, convert every second layer of logic into its DeMorgan's equivalent (i.e.  an OR gate with inverted inputs becomes a NAND and an AND gate with inverted inputs becomes a NOR).

 

5.  What is the difference between a latch and a flip-flop?

 

Flip-flops are triggered only on the clock edge (i.e. only accept data on the clock edge)

 

6.  Draw a timing diagram showing the operation of a negative edge tirggered D flip-flop.

 

7.  Draw the schematic for a positive edge triggered master slave D flip-flop using inverters and transmission gates.

 

8.  What are the functions of the two transmission gates in a transmission gate D latch?

 

One transmission gate either stops or allows new data to enter the latch.  The other transmission gate provides a feedback path for maintaining the stored value.

 

9.  Draw the schematic of an D latch using only transmission gates and inverters

 

10.  How do you turn on an NMOS transistor strongly?

 

Apply a gate to source voltage of approximately two or more volts (i.e. gate to source voltage should be significantly greater that the threshold voltage).

 

11.  How do you make a CMOS transmission gate?

 

Connect a PMOS and NMOS transistor back to back (i.e. connect their sources and drains together).

 

12.  Which are better at conducting logic low signals, PMOS or NMOS?

 

NMOS.  They are turned on strong when the drain and source are at logic low (typically 0 volts).

 

13.  Why is CMOS technology better than other technologies?

 

It offers good performance and generally lower power dissipation. More importantly, it offers very high levels of integration (i.e. you can put a lot of transistors on a chip).

 

14.  Draw and label the characteristic curves for an NMOS transistor.

 

15.  What is the typical threshold voltage of a PMOS transistor?  What does this mean?

 

-1 V.  The gate voltage must be at least one volt less than the source voltage to turn on the transistor.

 

16.  Draw the transistor schematic for a CMOS 3-input NOR gate.

 

17.  Draw the transistor schematic for a complex CMOS gate that implements the function !F = (A + B) * (C + D).  Where ! means inversion.

 

18.  What is the advantage of using both PMOS and NMOS transistors in a CMOS gate.

 

There is no DC power dissipation  (i.e. no continuous current).

 

19.  An NMOS transistor has a load resistor connect to ground.  It the transistor source is connected to ground and a gate voltage is applied to turn on the transistor, what output voltage and current do you expect?

 

The output voltage and current are both 0.

 

20.  If you decrease the load resistance, what do you expect to happen to a CMOS gate output?

 

The output current will be increased and the output voltages will be farther away from the supply voltages.

 

21.  If a CMOS gate with a logic low output can provide 10 mA of current at 0.25V, how much current can it provide when the output is 1V?

 

It depends on the transistor characteristics, but it would be less than 40 mA due to the non-linear characteristics of the transistors at high current levels.

 

22.  What does V_IL mean?

 

The maximum voltage that can be recognized  as a logic low input.

 

 

23.  If a circuit has V_IL = 1V, V_IH = 4V, V_OL = 0.5V, V_OH = 3.5V what are the lower and upper noise margins?  Is this a good circuit?

 

Upper noise margin is –0.5V, lower noise margin is 0.5V.  Bad circuit with negative noise margin (i.e. a valid high output may not be recognized as a valid high input even without any noise)