Classes are Every Tuesday and Thursday afternoon in Mackenzie 3269 from 2:35-3:55.
Labs/Group Problem sessions sets are every Wed and Fri from 9:05am 11:55am in either Minto Lab 6030 (odd weeks) or ME 4174 (even weeks). Check the calendar if you are unsure where the lab is each week - MC:Minto, ME:Mackenzie.
This is a tentative schedule and some of the lecture material may be shoved around a bit depending on how we are progressing through the material.
Final exam 50% open book
- The final examination is for evaluation purposes only and will not be
returned to students.
Midterm 20% open book
- This will be returned to the students
Lab-Prob 25% groups of three
- Interim reports and problems 25%/2.
- Final project report 25%/2. Final: half on technical, half on
organization, clarity and writing. See lab-section below for details.
Class quizzes, misc. (like a lab exam) 5% - Any unused part of this will be added to the interim report and problems weight.
Verilog Part 1 (Rev O) (21 pages)
Lecture 1
- words vs pictures
- syntax
- data types
- operators
- hierarchy
- structural vs procedural
- avoiding latches in procedures
- initial vs always
- Real Circuits: Big structures, small procedures
- Time @( ) vs #5 vs wait(signal)
Verilog Part 2 (Rev M) (22 pages)
Lectures 2, 3
- avoiding latches again
- synthesis of flip-flops and registers
- Finite state machines
- Coding FSMs
- Avoiding FSM coding errors
- The exception to the rule - Simple FSMs
- Synthesis - Logic inference
- trigger lists and latches
- functions
- flip-flops with resets and scan
- the great reset debate: synchronous vs asynchronous
- accidentaly making flip-flops
- to block or not-to-block ( <= vs = )
Design Flow (Rev G) (11 pages)
Lecture 4,5
- The Goal: GDSII (Layout diagrams)
- Specification
- RTL
- Synthesis
- Contraints
- Floorplanning
- Power Planning
- Design For Test (DFT) & Scan insertion
- Clock tree insertion
- Optimization
- Routing
- Extraction
- Signal Integrity Checks
- Design-Rule Check (DRC)
- Layout vs Schematic (LVS)
- Summary
Complete Digital Synthesis Tutorial (Documentation Only)
Vitesse Design Flow Example
Multiplier
Synthesis LAB
The Hardware Designer's Coding Laws! (must be used in lab)
Lecture 7
- Reset all flip-flops*
- Use active-low asynchronous resets*
- Signals that cross clock domains must be double-sampled
- Use as few clock domains as possible
- Do NOT use clocks or reset as data or enable signals*
- Don't gate clocks!*
- Use named notation when instantiating modules*
- Code one module per file, with the file name matching the module name*
- Keep the same signal name throughout the design hierarchy*
- Suffix names with _a for asynchronous signals, _n for active low signals
- All busses must be of form [n-1:0], with MSB on the left*
- Avoid latches*
- Avoid using the negative edge of the clock*
- Include all input signals in a C/L block sensitivity list*
- Ensure variables are assigned in all branches of a C/L block*
- In RTL, Never initialize registers in the decleration*
- Write FSMs in 2 to 3 seperate always blocks*
- Use non-blocking (<=) for registers and blocking (=) in C/L*
- Avoid long if-then-else statements*
- The same test-bench should be used for RTL and gate-level*
- The test-bench must never change inputs on the clock edge*
- The test-bench should only check outputs @(posedge) clock*
- The top test-bench must automatically determine whether the circuit
works*
Review of Digital Design Basics (Rev M) (24 pages)
Lecture 8
- Abstraction: Behavioural -> Structural -> Physical
- Other things: Circuit Design, Production Issues, Group Dynamics*
- 11 Less common topics covered in the course*
- Basic Switching circuits (ands/ors with ideal switches)
- MOS transistors: NMOS vs PMOS, Source vs Drain
- Threshold voltages: NMOS is good for pull-down, PMOS for pull-up
- Voltage loss from NMOS with feet in the air
- Threshold Voltage variation
- NMOS logic
- Combining NMOS and PMOS to create CMOS
- Demorgan's Theorem
- Transforming functions to gates*
- Example: Full Adder Carry Function, Self-dual functions
- CMOS Complex Gates - maximum size*
- Graphical Demorgan to split up large gates*
- Primitive gates/timing in Verilog (don't use)
- Verilog Timescale*
- Verilog 4 state values (0,1,x,z) and what they mean
- Building an XOR gate
- Verilog buffer, not, and 3-state gates
- Minimum, Typical and Maximum delays*
- Buffer/3-state construction to drive busses
Fractional Binary Numbers
More Simplified RC Notes
Page 1
Page 2
Page 3
Page 4
Verilog Part 3 (Rev Q) (26 pages)
Lecture 9
- Races due to blocking in flip-flops
- Multiple Assignments / driving an output in 2 places
- Full case vs Parallel Case
- case/casez/casex
- Unknowns/don't-cares in control and output
- Negative Numbers
- For Loops and their limits
- external: VPP verilog preprocessor
- Compiler Directives
- Using library components (eg. Designware)
- Part 3 Summary
Good Verilog References
On-line Verilog HDL Quick Reference Guide (S. Sutherland)
Verilog Quick Reference Sheet
Peter's Verilog Refernce
Digital Circuit Building Blocks (Rev L) (21 pages)
Lectures 10,11
- Dealing with Active Low signals
- Muxes: Operation and symbol
- Muxes in verilog - assign vs structural vs always block
- Transmission gate
- Transmission gate as a MUX
- Multi-input Muxes
- DeMux/Decoder
- Priority Encoder
- casez (x matches x, z or ? match anything)
- casex (x or z or ? match anything)
- Barrel Rotators and Shifters
- NMOS Logic pullup transistors
- Shifting/rotating in Verilog (watch out for -ve numbers)
- The logarithmic barrel shifter
- Logarithmic Circuits in General*
- Logarithmic Comparator
Adders (Rev T) (45 pages)
- T flip-flop binary counter
- Converting the carry to logarithmic delay
- Genertating intermediate carries
- 1-Bit Full Adder, Carry Generate and Propogate*
- 1) 4-bit ripple carry adder -> using generate and propogate*
- Derivation of the Carry-Lookahead adder
- Making a big carry-lookahead circuit
- 2) Cascading Carry-Lookahead blocks in a ripple
- 3) Mixing a ripple carry inside a carry-lookahead*
- 4) Brent-Kung Carry-Lookahead adder (hierarchical carry-lookahead)*
- 5) Carry Skip/bypass adder (carry-in -> carry-out of section is
fast)*
- 6) Carry Select adder (Compute for carry-in=0 and 1, then select)*
- 7) Conditional Sum Adder (Combination of carry-select and
carry-skip)
- 8) Carry Save Adder (Reduction of multiple input adder)*
- False paths*
- Non-Redundent Carry skip/bypass adder
- More on Carry Select and Conditional Sum adders
- Increasing stage length to reduce delay*
- Verilog adders*
- Negative Numbers*
- Subtraction*
- Finding the 2s complement*
Auxilliary notes on bit-serial adder, CSA adder, and multiplier* (Full long notes)
Page 1/2
Page 2/2
Screenshots of the Digital flow from RTL through to 'near' the end*
A Live Design Example: Signed Multiplier (12 pages)
- Directory Structure
- Code Structure for a large project
- How a signed multipler works
- Signed Multipler RTL
- A fancy self-checking testbench
- Vector Search routines and why they're usefull
Sequential Circuits (Rev I) (20 pages)
- the basic SR latch
- D latches and flip-flop
- Dynamic D-latch
- Static D-latch
- Clocked invertor D-latch
- MUX D-latch
- Master-Slave flip-flop
- the Enabled D flip-flop
- Verilog latches and flops
- Shift Registers
- Mobius/Johnson Counters*
More Counters (Rev J) (23 pages)
- Linear feedback shift register (LFSR)/Pseudo-Random Binary Sequence
Gen. (PRBS)*
- Binary Up-counter
- Binary Dn-counter
- loadable counters
- glitches in counters*
- Ripple Counter*
- Gray codes*
- Bit Serial Adder*
Defects and Fault Models (Rev H) (13 pages)
- Complete Tests vs Defect Based Test vs Fault Models
- CMOS failure Mechanisms
- Fault models of Defects
- Testing for Single Stuck-at faults
- Philosophy of Stuck-at testing
- Stuck-ats and fan-out
- Other Fault Models
- Faults for At Speed Testing
- Test Generation: Finding test vectors
- Test for At speed testing
Scan Tests (Rev L) (18 pages)
- Sequential Circuit Testing Problem
- Make the circuits pre-loadable
- Connecting the flops in a scan-chain
- Running a basic scan test
- Scannable flip-flops
- Multiplexed flops
- Dual-clock flip-flop
- Level Sensitive Scan Latches
- Comparing the scanable flops
- Mux-scan flip-flop problems
- gated clocks for partial scan
- other testing problems
Notes on interpreting a timing report from Cadence's PKS
We won't be coverting the notes below, but feel free to look through them.
Testing Outline (Rev D) (13 pages)
- Testing Purposes
- Production Testers
- Types of Digital Production Test
In this course the lab is to implement a Viterbi decoder, taking the design from specification, through RTL coding, synthesis, placement and routing.
It is a very intensive lab, and will be overseen by your TA.
The labs/problems MUST be performed in groups of 3! You are to submit to me your partners during Lecture 3 on Thurs Sept 16th. Those who have NOT submitted partners by that time will be forcefully married at Lecture 4 on the Sept 21st!
Refer to the course calendar for specifics, but generally speaking the weeks are broken down into Problems and Labs.
Problems require some thought/design work, wheras the Labs is when you actually sit down and code. For both the problems and labs a weekly report is due. In each case, you are expectecd to get together as a group and work on the problems/labs together. Though everyone is expected to contribute to each question/module, ONE person will be the lead for each question/section. The marks for each piece (good or bad), will be individually assigned. If you don't do your fair share of questions you will be penalized, to the credit of someone else in the group who picked up the slack. The intention is to mirror projects in the real world. For any project, the entire team will have a say, but at the end of the day it is the 'chip-lead' (the project manager) who is responsible for the failure or success of the product. The same will happen here - except on a much smaller scale. One person is the lead on each question/module, but all are expected to contribute!
Each week in the reports we expect to see who was the lead for each solution/module!
For lab related reports, we also specifically need to see:
- Code Listing
- Simplified Logic Digrams
- Testbench Listings
- Annotated Waveforms
Each week's report is due at the START of your problem/lab session the following week.
I've put together a tentative marking scheme for the final report. Tentative Final Report Marking Scheme and breakdown.
A common mistake is not including descriptions/diagrams of your circuits. If it is a verilog circuit, show the simplified logic diagram. If it is a testbench, show the simulation of the testbench against the circuit. Take a look at lab_template.txt to get a better idea about what you need. This example is for lab 2, but we're looking for the same sort of thing for each lab.
The problems and labs start with the Convolutional Encoder, then we
diverge into Synthesis of a pre-designed multiplier circuit before
returning to the Viterbi Decoder.
Viterbi
Lab Part 1/2
Viterbi
Lab Part 2/2 Undergoing revisions - but good up to pg 34 as of 9:02am WED morning Oct 20th!.
The
Multiplier Synthesis LAB,
files,
UNIX instructions, and
Course notes (12 pages)
Complete Digital Synthesis Tutorial (Documentation Only) Complete Digital Synthesis Software - Tarred,gzipped file, (also includes documentation)
Final Report format.
Practical Design Guidelines (.ppt)
Previous Years Q&A
Instructions for setting up/using NC-Verilog on UNIX
A free verilog simulator that you can intall and use at home.
Note on lab accessibility: The lab 6030 MC will generally be open during the day for extra lab time however, there are labs booked for other courses almost every afternoon. These people have priority. The 4th floor ME labs can also be used. A downloadable (easy to use) Verilog simulator is also provided so that you can work at home. This simulator is only usefull for small projects however, and will likely not work on your FINAL design all at once. Another option (if you have dialup access) is to telnet in to the unix systems and use the unix verilog compiler remotely (Verilog-XL). If interest is shown in this technique I'll arrange a short tutorial in the lab session. Bottom line is that all you need to work on the labs is a text editor, and occasionally a compiler.
Tips to get good marks (and make Reza's life easier)
1. Don't regurgitate what is not yours - reference the lab handout. I don't want to wade through pages of 'non-contributions.'
2. ALWAYS include code and make it nice
- KISS
- What can be said in pages of text is much more apparent through a couple lines of commented verilog
- Indentation is key
- Seperate combinational logic from sequential - always statements should be one of two forms
- Reset every flip-flop (in the same way)
- In general, shorter code is better - there are exceptions
3. Testbenches are as important as the code.
- Annotate waveforms, learn what cause and effect arrows are and use them EXHAUSTIVELY
4. Summarize the key results/specifications/design choices of a problem or report in a summary table.
5. Don't waste your time formating margins, picture spacing, fonts, etc... I'm a content man. It should be succinct.
As far as I'm concerned a DOS text printout in point form is ideal. Of course while this may not be the case in your career,
I'm of the belief that the engineer should do the engineering. The typesetter should do the formatting.
For the Vitesse bridge camp the students were responsible for bringing a 'Fun-counter' from RTL through gate-level
synthesis, floorplanning, placement, and routing. Screenshots of the process are
here.