97.478 Lab Q&A Page (with Lab Marks)

Questions and Answers

Question (Sep 24): I'm keen and want to put lots of information into the weekly reports. How is that treated?
Answer: As you might imagine there was a split decision on this and we've come to a great solution. In the core of the reports put ONLY what is asked for in a very CONCISE manner. We encourage EXTRA information to be put into an appendix at the back which will be 'checked' but not marked. Reference the appendix in the core of the report. Appendix information (per question) will likely result in a small amount of bonus marks.

Question: My partners and I did equal work on all parts of the lab/problem, is it acceptable to split conglomerate marks?
Answer: No! Although it is expected that you will work together on each question, ONE person must take 'sign-off' responsibility for that question. Sink-or-swim the marks go to him/her for THAT question.

Answer Not very formal - I want a cover page with your group info, the relevent code, an output log file with some annotation, and an annotated waveform for at least one of the cases. I don't need to see the state diagrams from Problem 1.
As far as an introduction/conclusion - after I rip apart (I mean mark) your first set of code you may weant to include something like 'Last lab I learned NOT TO ...' Point form is best. In the end (for the final report) you will need to create simplified circuit diagrams, discuss the operation, and various PROs/CONs about your particular design compared to other possibilities. You may want to start this early (eg. when you do the module), but I don't want to see them until the end. The less paper weight the better.

Question: I just have a quick question about lab 1 for 97.478. It mentions in the lab before question 1 that for the contraint 3 system you must have your test bench automatically compare our answer to the result we obtained from our student number. We did check our results against the student number we used in Problem Set #1, however the test bench we are handing in uses the data that was given in part 3 of the lab (since this way it should be easier to mark since the answers have been worked out already in the lab itself). Would you like us to also hand in the test bench with the data set to the student number we used in Problem set #1? And what does it mean to have the test bench automatically check that the results are the correct? Is it sufficient to have the output file display the z1 and z2 results to manually check the answers?

Answer As stated, your test-bench should automatically compare your results vs the expected values. Do this for both the given data and your student number. Also include a listing of the sampled values. Partial pseudo-code to do auto checking would go something like this:

    data_vector_1[15:0] = 16'b1101_0010_1100_0000; // the vector from problem 3
    data_vector_2[15:0] = 16'b0110_1100_0101_0000; // your student number vector
    expected_vector_1_z1[15:0] = 16'b1000_1111_0001_0000; // from problem 3
    expected_vector_1_z2[15:0] = 16'b1110_0110_0111_0000; // from problem 3
    expected_vector_2_z1[15:0] = 16'b(whatever you worked out by hand);
    expected_vector_2_z2[15:0] = 16'b(whatever you worked out by hand);
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    // now you need code to sample your results and check vs expected values
    always @(posedge clk)
      if(expected_vector_x_z1[i]!= current_z1_out_of module)
        $display("%t - ERROR: Sample did not match.", $time);
    always @(posedge clk)
      if(expected_vector_x_z2[i]!= current_z2_out_of module)
        $display("%t - ERROR: Sample did not match.", $time);

    always @(posedge clk) i=#1 i+1;
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Question: My answer from question 3 doesn't match. Why?
Answer: Could be many things. The likely suspects are:
- you may be sending the data in backwards
- the generating vectors are specified left->right for a system which shifts left to RIGHT - you may have them backwards.
- you may be sending data in while the system is in RESET -> it won't respond. You must clearly go through startup sequencing

Question: Do I really need a reset?
Answer: YES, YES and more YES! - the best are probably coded as asyncronous resets.

Question: How should I work the reset?
Answer: Initialize to 0, then make it high after #1, then drop it after a positive clk edge.

Question: Why should I go through such an intricate reset procudure?
Answer: If your reset is coded with always @(posedge rst ...) then (depending on the simulator), it might not recognize going from uninitialized to 1 as a posedge transition. We leave it high until after a clock edge to ensure that we clear any posssible syncronous reset flops in the system.

Question: I know it is going to come up in some state, and I don't care what - why spend the extra silicon area to put in a reset?
Answer: There are 2 related, simulation based issues. For sanity and test-bench re-use reasons we want the simulation to MATCH real-life. If we start from an unknown state this will not be the case. Second, the simulator will recognize a non-reset value as x -> now this goes into logic which propogates the x -> etc... They have a nasty habit of spreading. To prevent this reset all flops.