NC-Verilog is the new version of Cadence's Verilog-XL. It is much faster
since it compiles the code before executing it.
In theory - to simulate requires three seperate steps - compling, linking,
execution - each of which normally uses a seperate command. HOWEVER, we
are going to use NC-Verilog in Verilog-XL compatibility mode. Instead of
using:
verilog +options files.v
we use
ncverilog +options files.v
In the ideal world this would be it. But, unlike verilog-XL,
NC-Verilog needs a place to store temporary files and so we must create
this directory and tell ncverilog where it is.
Create a work directory: mkdir worlib
Now we need to create a file (in the current directory) which tells
NC-Verilog which work directory to use. Create a text file called
"cds.lib" with the following entry:
define worklib ./worklib
Finally, we need to create an empty file called "hdl.var" otherwise
NC-Verilog will get mad at us.
The unix command to create an empty file: touch hdl.var
You are almost ready. You have to set up some path information via a script file. Either use this
command every time you login, or add it to your .bashrc file in your root directory to execute
automatically for you each time.
source /CMC/scripts/setenv.cds.02.bash
So now you are set. You can run ncverilog and pump millions of bits
through in a minute or so.