Advanced Digital Electronics 

(ELEC-4708)

Notice Board

08 Dec 14: Assignment 4 uploaded. Please try the problems before the review session.

05 Dec 14: Final exam review session will be on Tue. Dec 9 at 5 pm in ME-4124

22 Nov 14: Assignment 3 uploaded

15 Oct 14: Assignment 2 uploaded

24 Sep 14: Assignment 1 uploaded

24 Sep 14: Lab1 Layout Tutorial Updated

24 Sep 14: TA office hours and location (ME-4174)

5 Sep 14:  Labs start  week of Sep 22.

Instructor

Maitham Shams

          Office Hours:  Wed and Fri  5:30 to 6:00 pm

                                 Wed and Fri  5:30 to 6:00 pm

Course Objectives

Lectures:  Analysis, Design and Implementation of Modern VLSI Circuits and Systems

Labs:   Use of a Modern IC Technology and Professional Cadence Tool for
                       Designing a Circuit from a Functional Description to Final Chip Layout

Expected Learning Outcome:

1. VLSI Functionality, Speed, Energy and Reliability
2. Device, Circuit, Logic and System Level Design
3. Circuit Simulation, Layout Editor, HDL Design (RTL) and Chip Tape-out

Course Outline

1. Review CMOS Logic
2. Review CMOS Latches and Flip-Flops
3. CMOS Layout
4. Review Hardware Description Language
5. MOSFET Current and Capacitances
6. Non-Ideal MOSFET Effects
7. CMOS Delay Estimation
8. Introduction to Logical Effort
9. Delay Optimization with Logical Effort
10. Power Estimation: Static and Dynamic
11. Low-Power Design
12. Static Combinational CMOS Logic Styles
13. Dynamic Combinational CMOS Logic Styles
14. Static and Dynamic Sequential Circuit Design
15. Testing and Design for Testability
16. Technology Scaling
17. VLSI Design Methodologies
18. VLSI Design Flow

Text Book

N. Weste and D. Harris, "CMOS VLSI Design: A Circuits and Systems Perspective," 4th Edition, Addison Wesley, 2011.

References

J. Rabaey, A. Chandrakasan, and B. Nikolic, "Digital Integrated Circuits," 2nd Edition, Pearson Education, 2003.

Marking Scheme

Lab                      25%              Bi-Weekly
                                                           Performed individually and reports are also submitted individually
          Assignments           5%              3 to 5 assignments
          Midterm Exam      20%             Closed Book. on Fri, Nov 7, 2014 .
                                                           Papers are returned to the students after marking
          Final Exam            50%             Closed Book. Papers are not returned to the students

Lectures

    In addition to the following slides, additional material and comments are given in class and students are expected to take notes.

Lecture 0

Lecture 1

Lecture 2

Lecture 3

Lecture 4

Lecture 5

Lecture 6

Lecture 7

    Lecture 8

Lecture 9

Lecture 10

Lecture 11

Lecture 12

Lecture 13

Lecture 14

Assignments

Assignment 1: due Fri, 3 Oct 2014, in class
Assignment 2: due Wed, 22 Oct 2014, in class
Assignment 3: due Fri, 28 Nov 2014, in class.
Assignment 4:

Resources

1. Text book's website
2. Solutions to odd-numbered problems

Labs

Labs are performed in MC-6030. The labs are officially scheduled biweekly in odd weeks. 

Lab Rules

1. Labs are performed individually to maximize the learning.
   
2. Attending labs are mandatory; students recieve a zero for the labs they miss.
   
3. Students must sign in, present any requested prelabs, demo the work at the end of the labs, and then sign out.
   
4. Lab reports are to be submitted individually on the next lab session.
   
5. Late lab reports after the deadline are penalized by 20% per day, counting weekends and holidays.
   
6. If a student submits a late lab report, the TAs must be notified through email to pick the report.
   
7. TAs mark and comment on the lab reports received by the deadline and return them to the students on the next lab session. 

      Lab 1> [Weight 8/25]

                Week 1: Mon Sep 22 and Thr Sep 25 (submit Part A separately in the box) [Weight 4/8]

                Week 2: Mon Oct 6 and Thr Oct 9 (submit Part B separately in the box) [Weight 4/8]

Lab 1 Instructions

Lab 1  Schematic Tutorial

Lab 1 Layout Tutorial 

      Lab 2> [Weight 17/25]

                  Week 1: Mon Oct 20 and Thr Oct 23; Deliverables 1 [Weight=1.5/17]

Week 2: Mon Nov 10 and Thr Nov 13; Deliverables 2 [Weight=3.5/17]

                   Week 3: Mon Nov 24 and Thr Nov 27; Deliverables 3 (Final Report) [Weight=12/17]

Lab 2 Instructions


Lab 2 HDL Simulation Tutorial

Lab 2 Synthesis Tutorial

Lab 2 Automatic Layout Tutorial

Verilog Review>

Verilog Guide; Introduction to Verilog; Verilog Slides from ELEC-3500: Part 1, Part 2, Part 3

Teaching Assistants

TA Name	Office	Extension	Email	Office Hours at ME-4174 (VLSI Lab)
Sukneet Basuta	ME-4134	x-8411	SukneetBasuta@cmail.carleton.ca	Mon   6 pm - 7 pm Wed   1 pm - 2 pm Thurs 3 pm - 4 pm
Ghazaleh Vazhbakht	TBA	TBA	GhazalehVazhbakht@cmail.carleton.ca	Wed 2 PM - 3 PM   Fri     2 PM - 3 PM Mon 4 PM - 5 PM

Note: TAs will be in the lab (MC-6030) in odd (lab) weeks at 1:30 pm on Mondays, and stay until 3:30 pm on Tuesdays.

Sample Exams

Sample Midterm Exam

Sample Final  Exam