Digital circuit design using verilog and logic synthesis, the electronic
properties of logic gates, electrical interfacing between logic families,
asynchronous to synchronous interfacing, clock distribution and timing, VLSI
The literature study is followed by a design or an analysis; or a comparative
analysis assignment. In this assignment it is expected that students will use
simulation tools (such HDL simulator, HSPICE) to re-analyse a circuit identified in the literature. It is expected that the critical
performance parameters (depending on the circuit it could rise/fall time,
power consumption, gate number complexity) be obtained. The topic could be
selected from the list provided or be proposed by the student for approval by
This course is intended for both senior M.Eng. and Ph.D. students in the Department of Electronics. It
covers all basic circuits currently in use for telecommunication
applications. Non-linear transistor characteristics are expressed in a closed
form. More complex telecom building blocks are then analyzed using these
basic transistor models. For oscillators and PLL circuit non-linear theory of
these devices is presented leading to derivations of closed form expression
for performance parameters such as oscillator Q, center frequency and PLL
bandwidth, capture range and the acquisition behavior. The material excludes
circuitsÆ behavior in the presence of noise.
This course builds up on the digital and analog design knowledge acquired in
the courses preceding. The course addresses the major design challenges faced
by digital designers today. These issues are in large part the consequence of
the increased on-chip frequency of operation and the speed of data exchange
on the PCB and on the backplane. Modern memory devices are overviewed.
Examples of memory and CPU interfacing are given.