Journal Papers:

  1. Bangli Liang, Dianyong Chen, Bo Wang, Tad Kwasniewski, Zhigong Wang, “Analysis, Optimization and Design of 2-2.8μm Stacked Multiple-Junction PIN GaInAsSb/GaSb Photodetectors for Future O/E Interconnections,” To be published in IEEE Transactions on Electron Devices, February 1, 2010. (#000909001)

  2. L. Zhang and T. Kwasniewski, “Comparison of amplitude-optimised bit-edge equalisation with pulse-width modulation in high-speed wireline application,” Electronics Letters, vol. 45, no. 3, pp. 189-191, January 2009. (#000909002)

  3. L. Zhang and T. Kwasniewski, “Optimal equalization for reducing the impact of channel group delay distortion on high-speed backplane data transmission,” AEUE (ELSEVIER) International Journal of Electronics and Communications, doi:10.1016/j.aeue.2009.04. 010. (#000909003)

  4. L. Zhang and T. Kwasniewski, “FIR filter optimization using bit-edge equalization in high-speed backplane data transmission,” (ELSEVIER) Microelectronics J., 40 (2009), pp. 1449-1457. (#000909004)

  5. D. Chen, W. Wang, and T. Kwasniewski, “Design considerations for a direct RF sampling mixer”, IEEE T. CAS II, vol. 54, no. 11, pp. 934-, 2007. (#04358612)

  6. Q. Du, J. Zhuang, and T. Kwasniewski, “A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction”, IEEE T. CAS II., vol. 53, no.11, pp. 1205-, 2006. (#04012377)

  7. M. Li, W. Huang, S. Wang and T. Kwasniewski, “0.18 um CMOS backplane receiver with decision-feedback equalization embedded”, Electronics Letters, vol. 42, no. 13, pp. -, Jun. 2006. (#01648567)

  8. S. Milijevic and T. Kwasniewski, “4 Gbit/s receiver with adaptive blind DFE”, Electronics Letters, vol. 41, no. 25, pp. -, Dec. 2005. (#01561763)

  9. M. Li, S. Wang and T. Kwasniewski, “DFE architectures for high-speed backplane applications”, Electronics Letters, vol. 41, no. 20, pp. -, Sep. 2005. (#01522158)

  10. M. Li, S. Wang, Y. Tao and T. Kwasniewski, “FIR filter optimization as pre-emphasis of high-speed backplane data transmission”, Electronics Letters, vol. 40, no. 14, pp. -, Jul. 2004. (#01315528)

  11. Jingcheng Zhuang, Qingjin Du and T. Kwasniewski, “Reduced in lock error DLL-based clock synthesizer with novel charge pump phase comparator”, Electronics Letters, vol. 39, no. 1, pp. 48-49, Jan. 2003. (#01182343)

  12. Lizhong Sun and Tadeusz A. Kwasniewski, “A 1.25-GHz 0.35-um monolithic CMOS PLL based on a multiphase ring oscillator” , IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 910-916, Jun. 2001. (#00924853)

  13. Miles A. Copeland, Graham P. Bell and Tad A. Kwasniewski, “A mixed-mode sampled-data simulation program” ,IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1098-1105, Dec. 1997. (#01052860)

  14. Manop Thamsirianunt and Tadeusz A. Kwasniewski, “CMOS VCO’s for PLL frequency synthesis in GHz digital mobile radio communications” , IEEE J. Solid-State Circuits, vol. 32, no. 10, pp. 1511-1524, Oct. 1997. (#00634659)

  15. Navid Foroundi and Tadeusz A. Kwasniewski, “CMOS high-speed dual-modulus frequency divider for RF frequency synthesis”, IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 93-100, Feb. 1995. (#00341735)

  16. Tom A. D. Riley, Miles A. Copeland and Tad A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis”, IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May. 1993. (#00229400)

  17. P. Mohanraj, David D. Falconer, and Tad A. Kwasniewski, “Baseband trellis-coded modulation with combined equalization/decoding for high bit rate digital subscriber loops”, IEEE J. on Sel. Areas in Comm., vol. 9, no. 6, pp. 871-875, Aug. 1991. (#00093097)

Conference Papers:

  1. H. Tai and T. Kwasniewski, “A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system”,  SOC Conference, 2011, (SOCC 2011), Nov 2011, pp. 114-117. (#06085130)

  2. B. Liang, D. Chen, H. Guo, B. Wang, Z. Wang and T. Kwasniewski, “Analyze and design 10-GHz 0.8-VDD -117dBc/Hz quadrature LC-VCO in 120nm CMOS technology”, Green Circuits and systems, 2010, (ICGCS 2010), Jun. 2010, pp 420-423. (#05543028)

  3. H. Guo, B. Wang, B. Liang, T. Kwasniewski and S. Robert, “Optimized LNA for analog RF front-end circuit in rain-machine interface”, Wireless Communications, Networking and Information Security, 2010, (WCNIS 2010), Jun. 2010, pp 147-150. (#05541746)

  4. A. Gabr and T. Kwasniewski, “Unifying approach for jitter transfer analysis of Bang-bang CDR circuits”, Electronics and Information Engineering 2010, (ICEIE 2010), Aug. 2010, pp Vol.2 40-44. (#05559711)

  5. H. Ho, V. Szwarc and T. Kwasniewski, “Design and implementation of a Multiplierless Reconfigurable DFT/DCT processor”, Circuits and Systems and TAISA Conference, 2009, Jun. 2009, pp 1-4. (#05290428)

  6. N. Kiddinapillai and T. Kwasniewski, “A 2–5 Gb/s fully differential 3X oversampling CDR for high-speed serial data link”, NORCHIP, 2009, Nov.2009, pp 1-4. (#05397815)

  7. D. Chen, B. Wang, B. Liang, D. Cheng and T. Kwasniewski, “Design and optimization of edge equalizer for high-speed electrical backplane”, Information, Communications and Signal Processing, 2009, (ICICS 2009), Dec. 2009, pp 1-5. (#05397646)

  8. R. Shariat-Yazdi and T. Kwasniewski, “A low complexity VLSI architecture for MIMO sphere decoding algorithm”, Circuits and Systems and TAISA Conference, 2009, Jun. 2009, pp 1-4. (#05290429)

  9. H. Guo, B. Liang, B. Wang, D. Chen and T. Kwasniewski, “Closed-Loop Gain Analysis of LC Quadrature VCO for the Accurate Prediction of Oscillation Frequency”, Microsystems and Nanoelectronics Research Conference, 2009,(MNRC 2009), Oct. 2009, pp 100-103. (#04230902)

  10. N. Kiddinapillai and T. Kwasniewski, “Jitter Tolerance Estimation of a 3X Oversampling CDR using Event-Driven Simulation,” Microsystems and Nanoelectronics Research Conference, 2009 (MNRC 2009), Oct. 2009, pp.136-139. (#04230904)

  11. Bo Wang, Dianyong Chen, Bangli Liang and Tad Kwasniewski, “Edge Equalizer for High-Speed Electrical Backplane Transmission,” Microsystems and Nanoelectronics Research Conference, 2009, (MNRC 2009), Oct. 2009, pp. 124-127. (#04230901)

  12.  Bo Wang, Dianyong Chen, Bangli Liang, Kwasniewski, T., “An improved equalization circuit for 10-Gb/s high-speed serial transmission over backplane channel,” International Conference on Communications, Circuits and Systems, 2009, (ICCCAS 2009), Jul. 2009 Page(s): 369 -372. (#04230906)

  13. Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Kwasniewski T., “A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel,” Canadian Conference on Electrical and Computer Engineering, 2009, (CCECE`09), May 2009,  Page(s):1221 – 1226. (#04230908)

  14. Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Kwasniewski, T., “Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel,” 11th International Conference on Computer Modelling and Simulation, 2009, (UKSIM`09), March 2009, Page(s): 574–578. (#04230912)

  15. Dianyong Chen, Bo Wang, Bangli Liang, Kwasniewski, T., “Transmitter equalizer optimization for 10-Gb/s data transmission through lossy backplane,” International Conference on Communications, Circuits and Systems, 2009 (ICCCAS`2009), July 2009 Page(s):373-376. (#04230905)

  16. Dianyong Chen, Bo Wang, Bangli Liang, Kwasniewski T., “A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously,” Canadian Conference on Electrical and Computer Engineering, 2009, (CCECE`09), May 2009, Page(s):1213 – 1216. (#04230909)

  17. Dianyong Chen, Bo Wang, Bangli Liang, Kwasniewski T., “A Simulator for High-Speed Backplane Transceivers,” 11th International Conference on Computer Modelling and Simulation, 2009, (UKSIM`09), March 2009, Page(s):589–593. (#04230911)

  18. Bangli Liang, Dianyong Chen, Bo Wang, Situ, G., Kwasniewski, T., Zhigong Wang, “A monolithic high modulation efficiency CMOS laser diode / modulator driver,” International Conference on Telecommunications, 2009, (ICT`09), May 2009 Page(s):361 – 363. (#04230907)

  19. B. Liang, D. Chen, B. Wang, T. Kwasnievski and Zhigong Wang, “An Improved General Model for Stacked PINPhotovoltiac Infrared Photodetectors,” Microsystems and Nanoelectronics Research Conference, 2009, (MNRC 2009), Oct. 2009, pp. 92-95. (#04230903)

  20. Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Kwasniewski T., “A full-rate truly monolithic CMOS CDR for low-cost applications,” Canadian Conference on Electrical and Computer Engineering, 2009, (CCECE`09), May 2009,  Page(s):1208 – 1212.  (#04230910)

  21. Liang B., Kwasniewski T., and Chen D., “A 42-Gb/s decision circuit in 0.13µm CMOS,” Proceedings of Sixth Annual Conference on Communication Networks and Services Research (CNSR`08), May 2008, pp. 339-342. (#04519878)

  22. Liang B., Kwasniewski T., Chen D., Wang B., and Cheng D., “1V supply CMOS DEMUX for 40-Gb/s optical communication systems,” Proceedings of 24th  Queen's Biennial Symposium on Communications, June 2008, pp.154-157. (#04563227)

  23. Liang B., Chen D., Wang B., Cheng D., and Kwasniewski T., “A 43-GHz static frequency divider in 0.13µm standard CMOS,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering 2008 (CCECE’08), May 2008, pp. 111-114. (#04564505)

  24. Liang B., Kwasniewski T., Wang Z., Chen D., Wang B., and Cheng D.,  “0.13µm 1.0V–1.5V supply digital blocks for 40-Gb/s optical communication systems,”  Proceedings of 2008 International Conference on Communications: Circuits and Systems (ICCCAS`08), May 2008, pp. 1393-1397. (#04657995)

  25. Liang B., Kwasniewski T., Wang Z., Chen D., Wang B., and Cheng D., “A monolithic 10-Gb/s CMOS limiting amplifier for low cost optical communication systems”, (APCC’08), 2008. (#04773694)

  26. Chen D., Wang B., Liang B., Cheng D., and Kwasniewski T., “Decision-feedback-equalizer for 10-Gb/s backplane transceivers for highly lossy 56-inch channels,” Proceedings of 2008 International Conference on Communications: Circuits and Systems (ICCCAS`08), May 2008, pp. 668-672. (#04657843)

  27. Chen D., Wang B., Liang B., Cheng D., and Kwasniewski T., “An improved simulation method for high-speed data transmission through electrical backplane”, (MNRC’08), Oct. 2008. (#04683388)

  28. Wang B., Chen D., Liang B., and Kwasniewski T., “Optimized CML circuits for 10-Gb/s backplane transmission with 120-nm CMOS technology”, (EDSSC’08), 2008. (#04760694)

  29. Wang B., Chen D., Liang B., and Kwasniewski T., “Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology”, (MNRC’08), Oct. 2008. (#04683408)

  30.  Dezhong Cheng, Bangli Liang, Dianyong Chen, Kwasniewski, T., “Optimize transistor size for FIR pre-emphasis with programmable coefficients,” 14th Asia-Pacific Conference on Communications, 2008, (APCC 2008), Oct. 2008, Page(s):1–5. (#04230913)

  31. Cheng D., Liang B., Chen D., and Kwasniewski T., “A reduced power 6-tap pre-emphasis for 10Gb/s backplane communications,” Proceedings of 24th Queen's Biennial Symposium on Communications, June 2008, pp.93-96. (#04563213)

  32. Shariat-Yazdi R. and Kwasniewski T., “Configurable K-best MIMO detector architecture,” Proceedings of 3rd International Symposium on Communications, Control and Signal Processing (ISCCSP 2008), March 2008. (#04537476)

  33. Li M., Kwasniewski T., and Wang S., “A 0.18µm CMOS clock and data recovery circuit with reference-less dual loops,” Proceedings of International Symposium on Circuits and Systems (ISCAS 2008), May 2008, pp. 2358-2361 (#04541928)

  34. Ho H., Szwarc V., and Kwasniewski T.,”A reconfigurable systolic array SoC design for multicarrier wireless applications,” Proceeding of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2008), August 2008. (#04616886)

  35. Shariat-Yazdi R. and Kwasniewski T., “A multi-mode sphere detector architecture for WLAN,” Proceeding of the IEEE International System on Chip Conference (SOCC 2008), September 2008. (#04641501)

  36. Zhang L. and Kwasniewski T.,”ISI mitigation using bit-edge equalization in high-speed backplane data transmission,”Proceeding of IEEE international conference on Communication, Circuits and Systems, May 2008, pp. 663-667. (#04657842)

  37. Siddiqui S. and Kwasniewski T. ”Ultra wideband wireless serial data communication at 10Gb/s in CMOS 90nm,” the 17th Conference on Electrical Performance of Electronic Packaging (EPEP 2008). (#04675896)

  38. Hagman M., and Kwasniewski T., “Two enhanced decision feedback equalizers for 10Gb/s optical communications”,(MNRC’08), Oct. 2008. (#04683394)

  39. Zhang L. and Kwasniewski T., “Using bit-edge equalization in high-speed backplane data transmission”, (CNC’08), 2008. (#04685108)

  40.  Shariat-Yazdi R. and Kwasniewski T., “Low complexity sphere decoding algorithms,” Proceeding of the IEEE International Symposium on Wireless Communication Systems (ISWCS 2008), October 2008. (#04726094)

  41. Wang X. J., Kwasniewski T., “A fast CMOS self-oscillating modulator for RF power amplifier,” Proceedings of Canadian Conference on Electrical and Computer Engineering (CCECE’07), April 2007, pp. 372-375.(#04232758)

  42. Wang X. J., Kwasniewski T., “A compensation way for a differential pair to achieve a high performance single-ended to differential converter,” Proceedings of Canadian Conference on Electrical and Computer Engineering (CCECE’07), April 2007, pp. 1137-1140. (#04232948)

  43. Shariat-Yazdi R. and Kwasniewski T., “A high performance VLSI architecture for MIMO detection in future WLAN receivers,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’07), April 2007. (#04233027)

  44. Shariat-Yazdi R. and Kwasniewski T., “Challenges in the design of next generation WLAN terminals,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’07), April 2007. (#04233028)

  45. Usama M. and Kwasniewski T.,” A 40-GHz quadrature LC VCO and frequency divider in 90-nm CMOS technology,”Proceedings of International Symposium on Circuits and Systems (ISCAS 2007), May 2007. (#04253321)

  46. Zhuang J. C., Du Q. J., and Kwasniewski T., “A 4GHz low complexity ADPLL-based frequency synthesizer in 90nm CMOS,” Proceedings of IEEE Custom Integrated Circuit conference (CICC 2007), September 2007, pp. 543-546. (#04405790)

  47. Zhuang J., Du Q. and Kwasniewski T., “A 3.3-GHz LC-based digitally controlled oscillator with 5kHz frequency resolution,” Proceedings of IEEE Asian Solid-States Circuits Conference (ASSCC 2007), November 2007, pp. 428-431. (#04425722)

  48. Shariat-Yazdi R. and Kwasniewski T., “Reconfigurable K-best MIMO detector architecture and FPGA implementation,” Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2007), November 2007. (#04445895)

  49. Li M., Kwasniewski T., and Wang S., “A 0.18µm CMOS receiver with decision-feedback equalization for backplane applications,” Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), Dec. 2006. pp 1039-1042. (#04145574)

  50. Du Q.J., Zhuang J.C., and Kwasniewski, T., “An anti-harmonic locking, DLL frequency multiplier with low phase noise and reduced spur,” Proceedings of IEEE Custom Integrated Circuit conference (CICC 2006), Sep. 2006, pp. 761-764. (#04115065)

  51. Zhuang J., Du Q., and Kwasniewski T.,”A timing jitter reduction technique in a cyclic injection clock multiplier for data communication system,” Proceeding of International SOC Conference (SOCC 2006), Sep. 2006, pp. 123-126.  (#)

  52. Zhuang J., Du Q., and Kwasniewski T., “Event-driven, modeling and simulation of a digital PLL,” Proceeding of International Behavioral Modeling and Simulation Workshop, Sept. 2006, pp. 67 – 72. (#04062054)

  53. Du Q.J., Zhuang J.C., and Kwasniewski, T., “A gigahertz cyclic injection DLL clock generator with an infinite acquisition range,” Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006), Aug. 2006, pp. 16-19. (#04267274)

  54. Zhang J., Kwasniewski T., and Mei H., “Analysis and simulation of phase noise in distributed oscillators,” Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006), Aug. 2006, pp. 312-316. (#04267137)

  55. Bereza Wm., Yuming T., Wang S., Kwasniewski T., and Patel R.H., “PELE: Pre-emphasis & equalization link estimator to address the effects of signal integrity limitations,” Proceeding of 43rd Design Automation Conference, July 2006, pp. 1013-1016. (#01688947)

  56. Usama M. and Kwasniewski T., “A 40-GHz frequency divider in 90-nm CMOS technology,” Proceedings of International North East Workshop on Circuits and Systems (NEWCAS 2006), Jun. 2006. (#04016960)

  57. Du Q.J., Zhuang J.C., and Kwasniewski, T., “A low phase noise DLL clock generator with a programmable dynamic frequency divider,” Proceedings of Canadian Conference on Electrical and Computer Engineering (CCECE’06), May 2006, pp. 701-704. (#04054686)

  58. Zhuang J., Du Q., and Kwasniewski, T., “An eye detection technique for clock and data recovery applications,”Proceedings of International Symposium on Circuits and Systems (ISCAS 2006), May 2006. (#01693794)

  59. Li M., Wang S., Kwasniewski T., and Tao Y., “A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18um CMOS technology,” Proceedings of ASP-DAC2005, Jan. 2005. (#01693799)

  60. Wang S., Mei H., Baig M., Bereza Wm., Kwasniewski T., and Patel R., “Design considerations for 2nd-order and 3rd-order bang-bang CDR loops,” 2005 IEEE Custom Integrated Circuits Conference (CICC 2005), San Jose, California, Sep. 18-21, 2005. (#01558669)

  61. Wang X., Kwasniewski T., “Low power design techniques for a montgomery modular multiplier,” 2005 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2005). (#01595443)

  62. Tao Y., Bereza Wm., Patel R., Shumarayev S. and Kwasniewski T., “A signal integrity-based link performance simulation platform”,  2005 CICC. (#01568770)

  63. Ahmed S. I., Orthner K., Kwasniewski T., ”Behavioral test benches for digital clock and data recovery circuits inverilog-A," Custom Integrated Circuits Conference, CICC 2005, Sept. 18-21, 2005 San Jose. (#01568664)

  64. Ahmed S.I., Kwasniewski T., “A multiple-rotating-clock-phases architecture for digital data recovery in verilog-A," Behavioral Modeling and Simulation Conference, BMAS 2005, San Jose, California, 22-23 Sept. 2005. (#20050404)

  65. Zarkeshvari F., Noel P., Kwasniewski T., “On delta-sigma fractional-N frequency synthesizers,” International Symposium on Signals, Circuits and Systems, ISSCS 2005, Jul. 14-15, Iasi, Romania. . (#20051115)

  66. Berndt C.E., Kwasniewski T., “A review of common receive-end adaptive equalization schemes and algorithms for a high-speed serial backplane,” International Workshop of System on Chip (IWSOC), Banff, Canada, July 2005.(#01530932)

  67. Li M., Wang S., Chen J., and Kwasniewski T., “Design and optimization of multi-tap DFE for high-speed backplane data communications,” IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, Canada, Aug. 2005. (#01517361)

  68. Zarkeshvari F., Noel P., Kwasniewski T., “PLL-based fractional-N frequency synthesizers,” 2005 International Workshop of System on Chip (IWSOC), Banff, Canada, July 2005. (#01530920)

  69. Li M., Noel P., Wang S., and Kwasniewski T., “Decision Feedback Equalization with Quarter-rate Clock Timing forHighspeed Backplane Data Communications,” Proceedings of the 9th International Database Engineering & Application Symposium (IDEAS’05), 2005. (#01530998)

  70. Zarkeshvari F., Kwasniewski T., ”Analog DLL-based period synthesis circuit,” International Conference on Communications, Circuits and Systems, (ICCCAS 2005), Hong Kong, China, May 2005. (#01495296)

  71. Zhuang J., Kwasniewski T., “A Multi-level Phase/Frequency Detector for Clock and Data Recovery Applications,” IEEE Canada, Conference on Electrical and Computer Engineering, 2005. (#01557056)

  72. Noel P., Zarkeshvari F., Kwasniewski T., ”Recent advances in high-speed serial I/O Trends, standards and techniques,” Canadian Conference on Electrical and Computer Engineering, IEEE CCECE05, Saskatoon, May 2005. (#01557213)

  73. Ahmed S. I., Kwasniewski T., ”An all-digital data recovery circuit optimization using Matlab/Simulink," International Symposium on Circuits & Systems, ISCAS 2005, May 23-26th, Kobe, Japan. (#01465628)

  74. Ahmed S. I., Kwasniewski T., “Overview of oversampling clock and data recovery circuits,” Canadian Conference on Electrical and Computer Engineering, IEEE CCECE05, Saskatoon, May 2005. (#01557348)

  75. Usama M. and Kwasniewski T., “Metastability analysis of CMOS current mode logic latches,” Canadian Conference on Electrical and Computer Engineering, IEEE CCECE05, Saskatoon, May 2005. (#01557269)

  76. Siddiqi, A. A.; Kwasniewski, T., “2.4 GHz RF down-conversion mixers in standard CMOS technology,” Proceedings of International Symposium on Circuits and Systems, May 2004, pp. 321 -324. (#01329005)

  77. Hui, Z.W.Y.; Kwasniewski, T.A., “A 10-Gb/s CMOS sample-and-hold phase detector using dual substrate technique,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’07), May 2004, pp. 1761-1764. (#01349756)

  78. Lei Lin; Noel, P.; Kwasniewski, T., “Implementing a digitally synthesized adaptive pre-emphasis algorithm for use in a high-speed backplane interconnection,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE’04), May 2004, pp. 1221-1224. (#01349615)

  79. Lei Lin; Noel, P.; Kwasniewski, T., “A VLSI implementation of an adaptation algorithm for a pre-emphasis in a backplane transceiver,” Proceeding of IEEE international conference on Communication, Circuits and Systems, June 2004, pp. 1429-1433. (#01346443)

  80. Usama M. and Kwasniewski T., “Design and comparison of CMOS Current Mode Logic latches,” Proceedings of International Symposium on Circuits and Systems (ISCAS 2007), May 2004, pp. 353-356. (#01329013)

  81. Miao Li; Kwasniewski, T.; Noel, P., “Symbol-spaced delay circuit design with half-rate clock timing for multi-taps FIR filter as pre-emphasis,”  Proceedings of .IEEE Asia-Pacific Conference on Circuits and, Dec. 2004, pp. 337-339. (#01412763)

  82. Abdul Shakoor, A.R.; Szwarc, V.; Kwasniewski, T.A., “High-speed Viterbi decoder for W-LAN and broadband applications,” The 2nd Annual IEEE Northeast Workshop on circuit and systems, June 2004. (#01359005)

  83. Zarkeshvari, F.; Noel, P.; Uhanov, S.; Kwasniewski., “An overview of high-speed serial I/O trends, techniques and standards,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’04), May 2004, pp. 1215-1220. (#01345340)  

  84. Noel, P.; Shariat-Yazdi, R.; Kwasniewski, T., “An overview of reconfigurable VLSI based signal processing building blocks for next generation wireless devices,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’04), May 2004, pp. 1207-1210. (#01345338)

  85. Usama, M.; Kwasniewski, T., “New CML latch structure for high speed prescaler design,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’04), May 2004, pp. 1915-1918. (#01347586)

  86. Jingcheng Zhuang; Qingjin Du; Kwasniewski, T., “Noise, spur characteristics and in-lock error reduction of DLL-based frequency synthesizers,” Proceeding of IEEE international conference on Communication, Circuits and Systems, June 2004, pp. 1443-1446. (#01346446)

  87. Miao Li; Kwasniewski, T.; Shoujun Wang; Yuming Tao, “FIR filter optimization as preemphasis of high-speed backplane data transmission,” Proceeding of IEEE international conference on Communication, Circuits and Systems, June 2004, pp. 773-776. (#01346294)

  88. Zoe Hui; Kwasniewski, T., “The application of a dual-substrate technique on a 10-Gb/s CMOS phase detector design,” Proceedings of 5th  International Conference on ASIC, Oct 2003, pp. 719-720. (#01277311)

  89. Jingcheng Zhuang; Qingjin Du; Kwasniewski, T., “A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer,” Proceedings of IEEE Custom Integrated Circuits Conference, Sept. 2003, pp. 301-304. (#01249408)

  90. Qingjin Du; Jingcheng Zhuang; Kwasniewski, T., “A delay-locked frequency synthesizer with low phase noise performance,” IEEE  Conference on Electron Devices and Solid-State Circuits, Dec. 2003, pp. 461-464. (#01283573)

  91. Jingcheng Zhang; Kwasniewski, T.; Haitao Mei., “A computational method in predicting distributed oscillator phase noise,” Proceedings of 5th International Conference on ASIC, Oct 2003, pp. 1025-1028. (#01277386)

  92. Jing Zhang; Haitao Mei; Kwasniewski, T., “Prediction of phase noise in CMOS distributed oscillators,” Proceedings of SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference, Sept. 2003, pp. 157-162. (#01244850)

  93. Lizhong Sun; Kwasniewski, T., “A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications,” Proceedings of IEEE Custom Integrated Circuits Conference, May 1999, pp. 265-268. (#00777288)

  94. Lizhong Sun; Kwasniewski, T.; Iniewski, K., “A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops,” Proceedings of International Symposium on Circuits and Systems (ISCAS 1999), June 1999, pp. 176-179. (#00780647)

  95. Sun, L.; Lepley, T.; Nozahic, F.; Bellissant, A.; Kwasniewski, T.; Heim, B., “Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis,” Proceedings of International Symposium on Circuits and Systems (ISCAS 1999), June 1999, pp. 152-155 (#00780641)

  96. Ho, H.; Szwarc, V.; Kwasniewski, T.A., “FPGA reconfigurability in the presence of logic and I/O faults,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’97), May 1997, pp. 740-743. (#00608347)

  97. Bhullar, G.S.; Szwarc, V.; Kwasniewski, T.A., “An architecture independent test methodology for SRAM FPGAs,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’97), May 1997, pp. 736-739. (#00608345)

  98. Sheikh, K.M.; Kwasniewski, T.A., “CMOS low-power microwave frequency prescalers for wireless applications,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’97), May 1997, pp. 637-640. (#00608316)

  99. Ho, H.; Szwarc, V.; Kwasniewski, T.A., “Pipelined digital design in SRAM FPGAs,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’97), May 1997, pp. 23-26. (#00614780)

  100. Thamsirianunt, M.; Kwasniewski, T.A., “CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications,” Proceedings of IEEE Custom Integrated Circuits Conference, May 1995, pp. 331-334. (#00518197)

  101. Kwasniewski, T.; Abou-Seido, M.; Bouchet, A.; Gaussorgues, F.; Zimmerman, J., “Inductorless oscillator design for personal communications devices-a 1.2 μm CMOS process case study,” Proceedings of IEEE Custom Integrated Circuits Conference, May 1995, pp. 327-330. (#00518196)

  102. Soto, C.P.; Saleh, R.; Kwasniewski, T., “Time warping-waveform relaxation in a distributed circuit simulation environment,” Proceedings of the 38th Midwest symposium on Circuits and Systems, Aug. 1995, pp. 338-341. (#00504446)

  103. Thamsirianunt, M.; Kwasniewski, T.A., “A 1.2 μm CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer,” Proceedings of IEEE Custom Integrated Circuits Conference, May 1994, pp. 383-386. (#00379683)

  104. Noel, D.P.; Kwasniewski, T.A.; Mahmoud, S.; Leblanc, W.P., “A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems,” IEEE 44th Vehicular Technology Conference, June1994, pp. 520-524. (#00345030)

  105. Ho Pon, C.R.; Saleh, R.; Kwasniewski, T., “Distributed circuit simulation using waveform relaxation in a slotted-ring architecture,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’94), Sept. 1994, pp. 545-548. (#00405809)

  106. Yaremchuk, G.; Pon, C.R.; Kwasniewski, T.; Goubran, R., “A novel slotted-ring architecture for parallel processing: an application,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’94), Sept. 1994, pp. 486-489. (#00405794)

  107. Noel, D.P.; Kwasniewski, T.A., “Frequency synthesis: a comparison of techniques,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’94), Sept. 1994, pp. 535-538. (#00405806)

  108. Noel, D.P.; Kwasniewski, T.A.; Castonguay, A.; Leblanc, W.P.; Mahmoud, S.A., “Software-to-hardware conversion: automating the process,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineers (CCECE’94), Sept. 1994, pp. 604-607. (#00405824)

  109. Watts, J.A.; Kwasniewski, T.A., “ROOMMS-a relaxation-based, object-oriented, mixed-mode simulator,” Proceedings of IEEE Custom Integrated Circuits Conference, May 1990, pp. 5.3/1-5.3/4. (#00124665)

  110. Mohanraj, P.; Falconer, D.D.; Kwasniewski, T.A., “Baseband trellis coded modulation with combined equalization/decoding for high bit rate digital subscriber loops,” Global Telecommunication Conference and Exhibition (GLOBECOM ’90), Dec. 1990, pp. 1669-1672. (#00116772)

  111. Mohanraj, P.; Joshi, V.; Falconer, D.D.; Kwasniewski, T.A., “Reduced-complexity trellis coding/decoding for high bit rate digital subscriber loop transmission,” IEEE International Conference on Communications (ICC 89), June 1989, pp. 526-530. (#00049752)

Book Chapter

  1. H. Ho, V. Szwarc, C. Loo, and T.A. Kwasniewski, Design and Implementation of a Multi-Carrier Demodulator,. in Recent Advances in Circuits, Systems and Signal Processing, edited by N. Mastorakis, and G. Antoniou, WSEAS press, pp. 44-50, 2002

US Patent Office Publications

  1. Publication number: US 2003/0141919 A1 (with Altera Corporation); Filing date: Filing date: Jan 31, 2002; Shoujun Wang, Tad Kwasniewski, Bill Bereza; Active peaking using differential pairs of transistors
  2. Publication number: US 2007/0002993 A1 (with Altera Corporation); Filing date: Jun 29, 2005; Shoujun Wang,Haitao Mei, Bill Bereza, Tad Kwasniewski; Clock data recovery loop with separate proportional path
  3. Publication number: US 2007/0069831 A1 (with Altera Corporation); Filing date: Sep 29, 2005; Tad Kwasniewski, William Bereza, Shoujun Wang, Muhammad Usama; Voltage controlled oscillator circuitry and methods

Patents Awarded

  1. US Patent No 06075419 (with PMC-Sierra Incorporation), 1999; L. Sun, T. Kwasniewski, K. Iniewski ,"High Speed Wide Tuning Range Multiphase Output Ring Oscillator"

  2. US Patent No 06301318 (with PMC-Sierra Incorporation), 1998; T. Kwasniewski, F. Wei, "Pipelined Phased Detector for Clock Recovery"

  3. US Patent No 5677650 (with PMC-Sierra Incorporation),   1997; T. Kwasniewski, M. Abou-Seido, S. Iliasevich, "Ring Oscillator Having a Substantially Sinusoidal Signal"

  4. Patent No. 00150611 (Conexant Systems), 2001 Inventors: T. Riley, T. Kwasniewski, T. Lepley; Delta-Sigma Modulator for Fractional-N Frequency Synthesis

  5. US Patent No. 5677650 (with PMC-Sierra Incorporation); Dec 19, 1995; Tadeus Kwasniewski, Maamoun Abou-Seido, Stephan Iliasevitch; Ring oscillator having a substantially sinusoidal signal

  6. US Patent No.  6075419 (with PMC-Sierra Incorporation);  Filing date Jan 29, 1999; Lizhong Sun, Tadeusz Kwasniewski, Kris Iniewski; High speed wide tuning range multi-phase output ring

  7. US Patent No. 6570518 (with Skyworks Solutions, Inc.); Filing date: Jan 4, 2001; Thomas A.D. Riley, Tadeuse A. Kwasniewski, Thierry Lepley; Delta-sigma modulator for fractional-N frequency

  8. US Patent No. 6970020 (with Altera Corporation); Filing date: Dec 17, 2003; Haitao Mei, Shoujun Wang,Mashkoor  Baig, Bill Bereza, Tad Kwasniewski; Half-rate linear quadrature phase detector for clock recovery

  9. US Patent No. 7061334 (with Altera Corporation); Filing date: Jun 3, 2004; Mashkoor Baig, Shoujun Wang, HaitaoMei, Bill Bereza, Tad Kwasniewski; Apparatus and methods for wide tuning-range ring oscillators

  10. US Patent No. 7143312 (with Altera Corporation); Filing date: Filing date: Dec 17, 2003; Shoujun Wang, HaitaoMei, Bill Bereza, Mashkoor Baig, Tad Kwasniewski; Alignment of recovered clock with data signal

  11. US Patent No. 7196557 (with Altera Corporation), Filing date: Jan 13, 2004; Tad Kwasniewski, Haitao Mei,Shoujun Wang, Mashkoor Baig, Bill Bereza; Multitap fractional baud period pre-emphasis for data

  12. US Patent No. 7224191 (with Altera Corporation); Filing date: Filing date: Nov 17, 2006; Shoujun Wang, BillBereza, Tad Kwasniewski, Mashkoor Baig, Haitao Mei; Differential signal detector methods and apparatus

  13. US Patent No. 7298636 (with Integrated Device Technology, Inc.); Filing date: Filing date: Mar 30, 2006; TingjunWen, Tadeusz Kwasniewski; Packet processors having multi-functional range match cells

  14. US Patent No. 7388443 (with Altera Corporation); Filing date: Apr 25, 2006; Haitao Mei, Shoujun Wang,Mashkoor Baig, Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski; Apparatus and methods for wide tuning-range ring

 


Copyright © 2012 All rights reserved