IV year project:

Digital speech processing in VHDL/Verilog for acoustical echo/reverberation Cancellation

Introduction:

This project involves making measurements of acoustics of a selected room (for example graduation hall) and developing real-time signal processing (in FPGA) to cancel room resonances. The A/D and D/A interfaces as well as FPGA to be programmed will be available in for of Xilinx/ Altera development board.The algorithm to be used is a series of three band-reject filters with settable bandwidth and centre frequencies. A programmable audio amplifier will also be available to facilitate early tests. 

Goal: The objectives of this project are:

       To develop a filter that would reduce selected room resonances/ reverberation,

       To develop efficient simulation algorithms and software tools for high-speed circuit analysis.

Requirements:

       Strong background in Electronics (specifically in linear systems, Laplace transform, filtering, z-domain filters),

       Interest and proficiency in Digital Design, FPGA,

       Strong analytical ability.

 

Following an initial common effort phase each member of the team will assigned a specific contribution.

There is an option to implement the algorithm on IPAD, using MACís IPAD development software.

 

 

Some useful Links:

  

Restricted area
(Exclusive use of Prof. Tad Kwasniewski's group)