Mixed Signal Design

Mixed Signal Design and Testing

A new area of research has been analog and mixed signal IC testing. In collaboration with Mitel Semiconductor Ltd., Micronet, SaskPower and researchers from the University of Regina (K. Runtz, R. Palmer) and the University of Manitoba (G. Bridges, D. Thomson), I have been the principal investigator in developing a novel method of testing analog and mixed signal ICs using periodic input stimuli and wide band undersampling.

In its simplest form, the testing procedure can be implemented in a design by adding two simple components on-chip: an analog switch to sample the response signal at a particular node under test, and a buffer to bring the sampled values off-chip. Using a sequential undersampling algorithm to control the switch allows high frequency signals to be mixed down in frequency and driven off-chip using a low bandwidth buffer. The utility of the procedure has been illustrated by measuring the frequency response, slew rate, and transient response characteristics for a number of CMOS circuits. Testing with a direct input to a sampling switch has shown that a 1.2 mm CMOS sampler can provide a 3dB bandwidth of 560 MHz with measured slew rates greater that 680 V/ms.

The undersampling approach has also been demonstrated as part of a mixed signal DFT architecture. By incorporating multiple samplers on-chip, access to a large number of high frequency internal test nodes can be provided with only a few external pins. Other advantages include small silicon overhead, low power consumption and potential for automated test point insertion. Currently, for CMOS circuits, there are no other suitable DFT techniques at these frequencies where even buffering signals off-chip or probing them can become difficult if not impossible.

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This page last updated on Janurary 28, 1997.