ELEC 4609 WINTER 2017
CHIP FABRICATION NOTES MARCH 24
A quick preliminary test today showed that the static PRSG and two dynamic PRSGs
were functioning correctly. More complete testing will continue on Monday.
Three wafers have now complete processing (one from each p-well dose).
The lightest dose is giving excellent nMOS and pMOS characteristics with low
subthreshold leakage when a small bias is applied to the substrate.
Here is a photo after metal!
nMOS test device subthreshold characteristics
For older reports see the fab blog archives .
IC DESIGN PROJECT REPORTS DUE MIDNIGHT TUESDAY MARCH 21
Individual reports are required. Submission is via CULearn.
Penalties for late submission will be significant after March 23.
Digital report guidelines
Analog report guidelines
LAB 3 BEGINS FRIDAY MARCH 17
Lab 3 will be covered in the next four formally scheduled lab periods.
Attendance is not compulsory but this material will be on the final exam.
MULTIPROJECT CHIP ASSEMBLY COMPLETE
The multiproject chip LEdit file can be downloaded here . Please check to make sure that your layout has not been
corrupted by the rectangle optimization processor. Photomask preparation is now nearly complete. A .gif image of the chip is available
IC DESIGN PROJECT SPECIFICATIONS
IC DESIGN PROJECT DEADLINES 2017
- January 12 Project sign-up (register on CULearn with partners' names, emails, proposed project)
- January 24 Full circuit schematic and SPICE simulation results due
- February 14 Final verified layout due
- Mid-March Comprehensive report on design due (individual reports!)
- Early April Brief report on test results (if fab run successful)
Photographs relating to microfab activities:
Pictures of circuit testing on prober:
Test MOSFET characteristics compared to models: