ELEC3500 - Xilinx
Project Navigator Tutorial.
This tutorial is
valid for Xilinx Project Navigator (ISE 8.2.02i), ModelSim XE/Starter III 6.1e, Spartan
III board.
·
Starting Xilinx Project
Navigator
·
Simulating the remaining cases
·
Downloading to the
Spartan III FPGA
·
Additional information for the TAs
Starting Xilinx Project
Navigator
The following window will open.
Select a project location on your W: drive (ie:
W:\Elec3500\). Any directories will be built automatically.
Enter a project name (ie: type your name).
Select HDL for the "Top-Level Source Type:"
Click "Next"
Click "Next"
Click
"Next"
Do
not “OK” yet.
About the Readback Options.
By
default, ISE does not create the necessary supporting files to enable the
Verify option during device programming.
It is not necessary to Verify
during programming and doing so will slow down the configuration process.
If
you want to use the Verify options, it is necessary to generate the appropriate
files as indicated above.
Simulating the remaining cases
Downloading to the Spartan III FPGA. (Field Programmable Gate Array)
OR
You can start the download by running the iMPACT:
Start
=> All Programs => Xilinx ISE 6 =>
Accessories => iMPACT
Click Next >
Click Finish
Click OK
This screen will show up if you did not setup the iMPACT device as indicated above iMPACT Device Configuration
Do
not panic the iMPACT will take care of this error and
use the JtagClk .
Additional information for the TAs
This section
contains some additional information that shouldn't be necessary to do the lab,
but may be helpful in preparing future labs or debugging students' circuits.
// updncounter.v -
Written by Gord Allan Jan 30/2003 for 350 lab 3.
module updncounter(clk, rst, pbl,
pbr, leds_out, status);
//
We need to call the main pins in and out of our design
the same as they are on the FPGA board
input clk; // from the clock pin on the function generator
input rst; // from the center push-button on the FPGA board
input pbl; // used for our count down control
input pbr; // used for our count up control
output [6:0] leds_out; // the lights on the FPGA board
output [3:0] status; //
additional active low LEDS available for troubleshooting
//
Finally, as in any language, there are some
declarations required.
wire cntdwn_from_pushbutton;
wire cntup_from_pushbutton;
reg [6:0] counter;
reg [6:0] next_count;
reg cntdwn;
reg cntup;
//
But, in our design they use different names, and so we must perform the
mappings.
assign status = 4'b1111; //
if the extra LEDS are not used turn them off
assign cntdwn_from_pushbutton = pbl; // map
them to the external names
assign cntup_from_pushbutton = pbr; // map them to the external names
assign leds_out = counter; // note that this will map all 7
bits
always @(posedge clk or posedge rst)
if(rst) counter <= 127; // default notation is in decimal
else counter <= next_count;
//
We use a seperate section to
compute what value the counter should take on, based on the inputs.
always @(counter or cntdwn or cntup) begin
next_count = counter;
if(cntdwn&~cntup) next_count =
counter - 1;
if(~cntdwn&cntup) next_count =
counter + 1;
end
/*
But,
there is a slight complication.
We
can't just use the cntdown signal directly from the
push-buttons.
The
resoning will be covered more in the lectures.
We
need to feed it through a flip-flop first.
*/
always @(posedge clk or posedge rst)
if(rst) cntdwn
<= 0;
else cntdwn <= cntdwn_from_pushbutton;
always @(posedge clk or posedge rst)
if(rst) cntup
<= 0;
else cntup <= cntup_from_pushbutton;
endmodule
#PINLOCK_BEGIN
#Mon Nov 29 13:29:45 2004
#PINLOCK_END
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk"
LOC = "D9";
NET "leds_out<0>"
LOC = "K12";
NET "leds_out<1>"
LOC = "P14";
NET "leds_out<2>"
LOC = "L12";
NET "leds_out<3>"
LOC = "N14";
NET "leds_out<4>"
LOC = "P13";
NET "leds_out<5>"
LOC = "N12";
NET "leds_out<6>"
LOC = "P12";
NET "pbl"
LOC = "L13";
NET "pbr"
LOC = "M13";
NET "rst"
LOC = "L14";
NET "status<0>" LOC =
"R16";
NET "status<1>" LOC =
"P15";
NET "status<2>" LOC =
"N15";
NET "status<3>" LOC =
"N16";
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
Test Bench File
updncounter_tb.v
module updncounter_tb;
reg
pbl; //
inputs to your circuit are declared as registers
reg
rst;
reg
pbr;
reg
clk;
wire [6:0] leds_out; //
outputs from your circuit are declared as wires
always #20 clk <= ~clk; // toggles
the clock every 20 time units
initial
begin // All initial statements start from the same time,
t=0.
clk=0; rst=0;
pbl=0; pbr=0; // initialize all inputs to something
@(posedge clk); // wait for the first clock edge
#5; rst=1; // turn on the reset
@(posedge clk); // wait for another clock edge
#5; rst=0; // turn off the reset
// it should be holding in reset
repeat(10)
@(posedge clk);
#5;
pbr =1;
// Now, the counter should be
merrily counting up
// we will wait until is reaches 69
and then switch directions
wait(leds_out==69);
$display("%t
- TESTBENCH: The counter has reached 69", $time);
@(posedge clk);
#5; pbl =
1; pbr= 0;
$display("%t
- TESTBENCH: Switching Directions", $time);
wait(leds_out==0);
$display("%t
- TESTBENCH: The counter has reached 0 - Finishing.", $time);
$finish;
end
// every time the clock falls, print out
the value of the leds
always @(posedge clk) $display("%t -
CLKSAMPLE: Leds sampled to be %d", $time, leds_out);
// set up statements to inform you when
inputs change
always @(rst) $display("%t - DATAMONITOR: rst signal changed to %b", $time, rst);
// and finally instantiate the device
under test (DUT)
updncounter
updncounter_instance(.clk(clk), .rst(rst),
.pbl(pbl), .pbr(pbr), .leds_out(leds_out));
endmodule
Xilinx Spartan 3 Family