ELEC 5705 Synthesizer Integrated Circuit Design (Last Updated March 31, 2005)

This is a page of information for my graduate course this term.  I will slowly update this page with information for this years assignments. 

The course will be held Tues and Thurs evenings from 7:30-9pm in room ME4332.  Notes are being printed and should be available to be purchaced from me in the first class.
Assignment #4 has now been updated for 2005.

The final exam will be on April 11, 2005 from 7pm -10pm. 

Course Outline

Assignment 1

Assignment 2

Assignment 3

Assignment 4

Final 2005

Final 2006

Final 2007

Final 2009


DFT Advice from Justin Abbott

Questions and Answers:

Simulation tip:  If the inputs to your PFD aren't high your simulation will die.

For assignment #1 you will all need 'ahdlLib'.  It may not automatically be in your library manager.  Therefore you will have to add it.  It is located in:

from there you should have everything you need to do the first assignment.

Q: Is equation 1.14 in the notes, the loop gain?
A: Not really.  It could be the DC loop again provided F(0)=1, but mainly it is a grouping of constants to make 1.13 easier to read. 

Q: Is equation 1.16 the open or closed loop gain?
A: It is the closed loop gain. 

Q: Are Lock Range (Johns and Martin text book), Synchronization Range (Blanchard text book), and loop bandwidth, the same thing?
A: No loop bandwidth is related to wn and the dampening constant.  Lock range in integrated circuits like the ones we will be dealing with is primarily determined by the VCO tuning range which is why this hasn't been mentioned more. 

Q: The course notes don't explicitly define what loop bandwidth is, can you define it?
A: The formula is given in 1.33.  If you are looking for deeper meaning then you can define loop bandwidth as the frequency at which the phase gain of the system is down by 3dB.  Roughly, below the loop bandwidth the output phase will track the input phase, but above the loop bandwidth it will not. 

Q: What does the natural frequency tell us about the loop?  What are typical values for the natural frequency for synthesizers?
A: Natural frequency is related to the loop bandwidth and therefore gives us some idea of the phase response of the system as well as phase noise characteristics. Natural frequencies in synths.  can be anywhere from a few hundred Hz to probably about 1MHz (depending on the application) but in theory can have any value desired. 

Q: Can we use the "freq_phase_detector" ahdl component from the Cadence ahdlLib library?  Or do we have to use the PFD you handed out in class?
A: If you verify that it behaves the same way, but be sure it does! Probably safer to use the one in class.

Q: Do we have to allow for process variation tolerance on the VCO (Kvco), similar to the example given on page 20 of the course notes?  You gave a number of 10% extra on the tuning range.  So instead of using Kvco=100MHz/V we should use 110MHz/V.

A: You should use 100MHz/V. 

Q: Which equation should we use from Equation #1.33 on page 18 of the course notes?  Equation 1.33a produces very different values from 1.33b for small damping factor values.

A:  They are both estimates that will diverge at lower dampening constants. The one on the right is probably a little less approximate.  

Q: Would you like to see plots for question #3 in assignment #1?

A: Absolutely!

Q: Does it matter whether I use the nfet or nfetx from the sige5am library, for building PFD and CP?

A: The only difference is only weather or not the substrate connection is brought out explicitly or not.  Either should work. 

Q: I ran a DC simulation using the nfetx, and the reported tox was 8.8nm, does this seem correct?  I'm
trying to calculate Cox and the voltage swing v1 (from equation 2.21 in the course notes).

A: As far as I know the models should be accurate. 

Q: What is the minimum transistor Length for an nfet transistor in this technology?  

A: This is a 0.5um technology. 

Q: Could you describe a process about how we should size the transistors for the PDF and CP?

A: This is the assignment.  The whole challenge is to figure out how to size everything in the circuit.  Telling you this wouldn't leave you with much work to do.  I have done my best to outline concerns that you need to consider in the notes. 

Q: Most of the course notes for the Charge Pump section focus on using nfets.  Would you recommend
building the Charge Pump from nfets?  I know we are free to do whatever we like.

A: This is something you should explore.  In some technologies pfets have lower 1/f noise so they may be a better choice.  Often you need both so there is no choice here, but it depends what topology you pick. 

Q: If I build the CP using nfets then I believe that it would be best to build the PFD using nfets.  This
would reduce potential problems (voltage level matching, timing) between the PFD and CP circuits. Would you recommend using a Level Shifter/Buffer to interface between the Divider (bipolar) and PDF (nfet) rather than in between the PFD and CP.

A: Without seeing a specific circuit this is a difficult question to answer.  Level shifting isn't usually that hard, and often the fets are a little more forgiving in terms of what DC levels they see so I don't think this should be a major problem for most. 

Q: Would you recommend using a single-ended or differential circuits for implementation of the PFD and CP.

A: I would expect that since I have stressed CML in the course that most will choose this route, but you are free to do either.