-- Bridge Camp 2000 --

Funding Help For Small Companies

The Bridge Camp

Contents of This Document

• Format of the course
• A brief description of the two courses.
• Content of Course I: Digital IC Aspects.
• Content of Course II: Analog Aspects.
• Course I: Industrial Lectures and Site Visits.
• Course II: Industrial Lectures and Site Visits.
• The Course Project.
• The instructors for Carleton

Format

There is a two-week analog ASIC design and a two-week digital ASIC design course.
In 2000 the analog and digital courses will run concurrently, May 29 to June 9.

• This allows say a digital students to substitute an analog lectures if the digital topic is well known to him/her.
• It will be much better in integrating the the analog and digital parts of the project.
• Unfortunately a student cannot take both courses at one site. However the McGill and Carleton Camps were arranged back-to-back. Thus a student can take both courses over a four week period by moving from Montreal to Ottawa.

A brief description of the two Carleton courses.

1. The mostly digital course takes students from a customer's "fuzzy specifications" through high-level simulation (Simulink) to a circuit design for standard-cell ASIC with a side look at FPGA implementation. The design at Caleton will be done using Verilog. Emphasis will be on writing synthesizable code even starting from the initial simulation phase. Possible problems with clocking, testing, off-chip inputs will be treated. The chip will be taken through to final tape-out using Synopsys and Cadence tools. The course is given by the faculty at the University who are involved in VLSI design, but are supplemented by many industrial speakers who stress concepts such as customer-owned tooling, intellectual property, packaging, testability and various cost-time trade-offs.
2. The analog-layout-fab course gives an introduction to analog circuits: op-amps, switched-capacitor, analog-to-digital conversion, RFIC, process basics and memory internals. Another major empasis is the analog side of digital; gate speed and loading, failure modes (e.g. hot-carriers, electromigration, and latchup), transmission-line effects, package models and ESD. They will design and layout the analog parts of the project, and merge them with the previously designed digital parts. At this stage, floor planning, layout, extraction, production test, packaging, and interfacing with a foundry will be considered.

The tools used are Synopsis DA, Cadence Verilog XL, Simulink, Cadence Analog Artist and HSpice.

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Course Content

Course I: Digital IC Aspects

CMOS Process Overview

CMOS process; Steps in deep submicron fabrication. Silicon Run video with many "real time" comments. Where digital circuits are going; SIA Road map. (Process 1, GT).

CMOS Review

Gate properties; delay, loading, fan out, fan in, power, gate construction. Gate properties in Verilog. (Digital 1, JK)

Standard blocks, Function and Structural Verilog Examples

Mux, demux/priority encoders, shifters, barrel-shifters. Verilog models. (Digital 2, JK)

Standard Blocks and Procedural Verilog

Counters: binary, Gray-code counters, pseudorandom (LFSR) and applications. Procedural Verilog models. (Digital 3, JK)

Synchronous machines and Verilog for Synthesis

FSM, state encoding, and Verilog. (Digital 4, JK)

Testing Overview

Faults and defects, fault modelling, ATPG, sequential test, scan, BIST, SCANBIST, boundary scan. (Digital 5, RM)

Verilog HDL as a language

Synthesis vs simulation: Gotcha's, asynchronous circuits, double clock example, ripple-counter code, test-bench code, coding style, examples (Digital 6, JK).

Synchronous clocking

Skew, optimization for timing, false paths, harmonically-related clocks, resynchronization, skew-correction latching, clock gating, arbiters. (Digital 7, JK)

Avoiding "work mostly" circuits

Asynchronous inputs, safe state-assignment, synchronizing flip-flops, safe reset circuits. Avoiding multiple-bit input problems; hand-shaking, debouncing, Gray codes. Leads into Digital 13, metastability.(Digital 8, JK)

Metastability.

Exponential model, MTBF, maximizing MTBF, safe state assignments, arbiters. Short lecture. (Digital 13, JK)

Clock distribution:

Clock trees, central clock distribution, line-widths, buffering principles. Power considerations. Grover loop. (Digital 9, JK)

ASIC Implementations: FPGAs:

Standard-cells, gate arrays. FPGAs, design cycles compared. FPGA architecture: Technology (fuses, antifuses, SRAM, charged gates). Components (logic elements, IO blocks). Performance (routing, logic vs ff). (Digital 12, RM)

Phase-Locked Loops and Applications.

Components: phase detectors and charge pumps, oscillators, dividers. Applications: clock-recovery, carrier recovery, frequency synthesis.(Signals 1, CP)

Digital Signal Processing.

Significance of the math: aliasing, accurate interpolation, possible nonlinear interaction. Complex resonators: poles-zeros and structure of simple filters. Biquads, cascaded filters, the reverb/comb filter, linear-phase/all zero/FIR filters. Adaptive filters, the LMS algorithm. Quantitization, modelled as noise, problems with model, limit cycles, scaling, noise shaping. (Signals 2, CP,JK))

Memories

Block-level internals; commodity SRAM, DRAM, SDRAM interfaces; memory in a logic process, memory in FPGAs. (Memory 1, , RM)

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Course II: Analog Aspects and Fabrication

Overview of Analog.

Why analog? Design and Layout Features of MOS: fets, caps, res, diodes. Analog blocks: voltage references, general properties of differential circuits.(Analog 1, CP)

Operational Amplifiers, Design, Simulation and Layout.

Building Blocks: current sources, gain stages. Types: two-stage, telescopic, folded cascode. Design Considerations: noise, gain, slew rate, bandwidth, stability, common-mode considerations.(Analog 2, CP)

Switched-Capacitor Circuits:

Basic concepts, differential circuits. Multi-phase clock generators. Pedestal effects, Clock feed-through, Noise (KTC noise). (Analog 3, CP)

Data Conversion.

Digital-to-Analog: R-2R ladder, current-steering, linearity. Analog-to-Digital: Successive approximation, flash converters, two-stage flash. Oversampled A-to-D: Concepts, noise shaping, 1st order, higher-order, MASH. (Analog 4, RM))

Overview of RFICs and Broadband Challenges and Techniques.

Low-noise amplifiers, mixers, oscillators, power amps, synthesizers, on-chip inductors, packaging. High-frequency simulation and modelling. (Analog 5, CP)

Memory Testing

Memory testers fault models, conventional tests. RAM in logic, RAMBIST. (Memory 3, JK)

Dynamic logic

Gate types, latch types, interface problems. Uses for fast high-density logic. Less aggressive uses: resynchronizing latches, reduced power TSPC flip-flops. (Digital 10, JK)

Layout Considerations and Reliability:

Standard cells, pads, protection, buffers, EMI, grounds, power, latchup, electromigration. (Digital 11, GT and RM)

Submicron CMOS Process Steps.

Reasons behind design rules, scaling, component matching. Choosing technology, bipolar/CMOS/biCMOS/SiGe. Analog design in a digital process.(Process 2, GT)

Real Submicron MOSFETS

MOS review, short-channel effects, hot carriers, sub threshold operation, velocity saturation. Advanced SPICE models.(Device 2, GT)

Layout 1

Lab talk: Floorplanning, design rules, extraction, verification, LVS.

Layout 2

Lab talk: Good layout, VDD & VSS, electromigration, placement, capacitors, crosstalk, grounds.

Course I: Industrial Lectures and Site Visits. Description

Designing Products that Win.

Moore's technology adoption life cycle, time-to-market, immature-mature products, technology-design-customer interaction. (Jim Roach, Tundra)

The Semiconductor Design Business

          Technology market drivers, good and bad examples of products, leading edge vs bleeding edge.(Dennis Colburn, DC Technologies)

Team Project Management

People-oriented and task-oriented persons, four-quadrants of personal style. (Tony Stansby, SMC)

Digital IC Testing in a Business Environment

IC product development cycle, tester hardware and signals, typical tests, test fixtures, characterization, impact on business.

(K. Fai Chen, Mitel)
Shrinking Technology
        Efects on design, CAD, and designers. (Stan Mazor, Cadabra)

Site Visit

Production fabrication and testing lab. (Nortel Networks)

Design Analysis and Intellectual Property.

        Protection of IP, patent uses and limitations, reverse engineering, student analysis from photos. (L. Lam, Semiconductor Insights)

Design Reuse

Design reuse, virtual components,  business and legal issues, design-for-reuse/design-with-reuse. (Parvis Yousefpour, Nortel Networks)

Design for Testability and Reliability

Testability, reliability, pure synchronous design, scan, BIST, JTAG and board testing, (Karl Siemens, Telexis)

Reworking/ Testing, Microsurgery.

Methods of repairing prototypes and capabilities of a reworking laboratory. (M. Simard Normandin, Nortel Networks)

Course II: Industrial Lectures and Site Visits. Description

Issues in Analog Design

Design flow including humans, models, tool interaction, common gotcha's -amplifier loading, power leads, parasites, digital models aren't, suspect transistor models, matching is not well known, simulate power up and down...-, document your design concepts (Was to have done in '99 by Ed MacRobbie, Philsar)

Practical Mixed-Signal Test

Comparing costs -pins vs area, yield vs fault coverage, area vs time-to-market, area vs test time-; analog test methods -P1149.4 mixed bus, mixed BIST 3 examples. (Was to have done in '99 Steve Sunter, Logic Vision)

Phase-Locked Loops

Uses, basics, VCOs, loop dynamics, phase-frequency detectors, charge pumps, delay-locked loops. (Was to have done in '99 by Stanly Ma, Mosaid)

Reverse Engineering Lab

Tour of Semiconductor Insights analysis laboratories.

Rework/Cost-Reduction

For high volume, fast ramp-up, long life products. Improving process, die size, package, test-time, yield. ( Was to have been done in '99 by Ray Wong, Nortel Networks)

Packaging

SMT families, parasites and noise, thermal, moisture, esd, handling and soldering, MCMs telecom packaging.

(Was to have done in '99 by Reg Simpson, Nortel Networks)

Memory

Static and dynamic ram, principles and innovations especially embedded memories. (Was to have done in '99 by Peter Gillingham, Mosaid)

Analog design traps

Substrate emmisions, thermal problems, power supply noise, package problems. (Was to have done in '99 by Tony Brown, Nortel Networks)

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The Course Project

The project is a mixture of analog and digital parts. The digital part simple enough (1000-3000 gates) to be completed in two weeks albeit with considerable coaching. The project should ideally:

• Do some signal processing.
• Use an A-to-D or D-to-A.
• Be at a speed which is too high to do directly in software.
• Be done at a speed where some consideration must be given to timing, impedance matching, and metastability.
• In addition a computer interface would be desirable but is not part of this years project.

The basic analog parts are:

• an op amp
• a comparator.

A very basic op amp is designed. Then attention is given to adjusting a library model to give good performance. These parts are used to build an oversampled d-to-a converter.

We force attention to milestones; the groups present their own management plans, which have to pass review, but there are "make/buy" decision points programmed in; if they're behind schedule, they have to "buy" a piece of design from a competing group or "off the shelf" from the camp. The groups do treat the design as noncompetitive. All students attend the design reviews of other groups and are encouraged to talk over problems with other groups. Also camp staff are available to give help and advise for more than a reasonable time each day.

This year's project will be a spread-spectrum receiver-transmitter. This project has been used since 1998 at Carleton and turned out to be a close match to the students abilities plus of topical interest to students in communications. The first course designed the spreading and QPSK modulators. They also designed a correlator for the receiver which was the hardest part of the digital project. The analog course adds an analog input with an oversampled A-to-D, which used the op-amp and comparator. Pads and a final output integrator were also added to the digital circuit. Possible RF portions were discussed but were not part of the project.

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Carleton and the Instructors

Carleton- A Hotbed for VLSI and Communications

Carleton Electrical Engineering, largely because of its proximity to large hi-tech companies, has specialized in VLSI, telecommunications and computers. Its faculty are noted for innovations such as the switched-capacitor filter, and the Boothroyd transistor models. Almost all the faculty are involved in joint research with hi-tech companies, and graduate students in VLSI often have an industrial mentor for their program.

The Academic Instructors

Prof. Calvin Plett will be teaching analog design. Engineers from the Ottawa area may be aware of his very popular graduate course on RF IC design. His teaching style and the way he relates it to his extensive practical experience tend to overfill his courses. His research and teaching cover switched-capacitor and analog filters, phase-locked loops, and A/D converters. He also "coaches" the "stress relief volleyball" between bridge-camp lectures.

Exposure to appropriate semiconductor and IC fabrication concepts will be given by Prof. Garry Tarr He has worked with SOI CMOS, and Si-Ge. Garry is in charge of the Carleton fabrication lab which has CMOS capability and can use electron-beam write to achieve a 0.2mm feature size. For more about the laboratory check the fab's web page
Check Garry's web page for a lot about canoeing in Algonquin Park.

John Knight is the professor who will be teaching much of the digital-circuit design, testing and layout. John has taught digital design and testing courses at Carleton and at Nortel and has won several teaching awards. His research interests centre on low-power circuitry and behavioural synthesis. His students also know him for metaphors like "blaspheming the clock."

Prof. Ralph Mason came Carleton from the University of Regina where his main research depended on circuits implemented as ASICs and as FPGA. At Carleton he has supervised many graduate students doing ASIC designs and has done extensive consulting on mixed-signal ASICs at Philsar.

If you can't find Tom Smy in his office, check the squash court. Tom is a metalization specialist who applys his knowledge to interconnects, on-chip inductors and CAD. Last year he gave the Camp an overview of deep submicron interconnect especially how it effects design.

Trevor Rainey of St. Lawrence College will manage the camp again this year. Trevor keeps the lecturers on topic, watches for battle fatigue, coordinates with industry about students and speakers, and sprays WD40 on the rough spots. In his other job, he coordinates a very successful industry-college joint project program.

All of the teachers have been given consistently high teaching ratings by their students.
 
 

© 2000 Strategic Microelectronics Consortium and Carleton University

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