97.583: Digital Circuit Design and Synthesis

                                Last upgraded  Dec. 14, 1999.

Examination

At 18:00 on Dec 14 in room 4332 Mackenzie Engineering: 
3 hours, openbbook.

Course Outline

The '583 course description tells potential students what to expect as much as one page can.

Course Assignments

The 1st assignment (due Tue., Sept 23.)

The two files for the first assignment are aprog1.v and aprog1.tst
Netscape users can download them by doing < shift>< click> on the file name above.
There is a bug in the program. If you simulate it you should see unknowns in one of the variables. The assignment for Tue., Sept. 21, '99 is to find the bug and write a one paragraph description of the cause.

The 2nd assignment (due Thur., Sept. 30, 1999)

Write a 2-bit bit-serial adder in Verilog.

input [1:0] A,B; // The two 2-bit numbers to be added.
input C0; // The original carry in.
output [1:0] S; output Cyout; // the three-bit output is {Cyout,S}

In clock cycle t0:

it reads in C0, A0, B0 and outputs garbage.

In clock cycle t1:
it reads in a new C0', A0', B0 and A1, B1, outputs S0 and garbage.

In clock cycle t2:
it reads in a new C0'', A0'', B0'', A1', B1' and outputs S0', S1 and Cyout.

In clock cycle t3:
it reads in a new C0''', A0''', B0''', A1'', B1'' and outputs S0'' S1' and Cyout'.

In clock cycle t4:
it reads in a new C0'''', A0'''', B0'''', A1''', B1''' and outputs S0''' S1'' and Cyout''.

. . .
This is a better bit-serial adder description than the one written on the board. That one put in a new input every second cycle and would need extra delays.
You may do either.

The 3rd assignment (due Thur., Oct.  7, 1999)

Prob. 3.4. From p. 62 of the "Making Asynchronous Signals Acceptable in Synchronous Circuit" notes.
 

The 4th Assignment (due Tue., Oct. 21, 1999)

The Tug of War pushbutton input circuit is described at the end of the "Making Asynchronous Signals Acceptable in Synchronous Circuit" notes. Consider the case where the tie state 11 is not allowed even for an instant.  If the two state outputs are (1/2 1/2), the states must never be taken as (1,1) at the outputs by any reasonable circuit. Design a gate-level circuit and, where the gates are not standard CMOS gates, a transistor level circuit. As an example, consider the arbiter discussed at the end of the notes on metastability.

The 5th Assignment (due Tue., Oct. 26, 1999)

    In problem 3.4. from the 3rd assignment, the signal is coming in in packets at rate  omega-delta. This is marginally different from rate w. The bits may not come in at omega/2 say.
Using a debounce solution the data must be at omega/2 or less or there is no way to debounce it. Thus debouncing is not a good solution. Also to read from a fifo it takes a definite time. It may be a whole clock cycle, it may be a fraction (say half) a cycle. You may decide what to use. However it cannot be a vanishingly small time. I suggest you arrange the circuit to give a whole cycle to read the fifo no matter what the phase relation is between the two clocks..
    Also you need to define how the fifo works. One method is that the write pointer points to the next empty cycle when idle. The operation of a write is "write, then increment" The read pointer must be arranged to read the top word if nothing is being written.  One way to do this is to "increment, then if no address conflict, read."  One student pointed out that this means that reset will have to be different for the read and write pointers. Perhaps a better read instruction would be "if no conflict read, then increment."
    A sheet of paper was given out in class giving a possible  circuit to solve the above problems.  Rick noted there should be an enable signal to stop the input counter if no packet is coming in. The assignment was to modify the circuit if necessary so that one will never read and write form the same fifo location even if the write counter changes on or near the omega clock edge.

The 6th Assignment (due Thur., Oct. 28, 1999)

    Draw a space-time diagram for a double-latch circuit including the little blocks representing tCHQV and setup times.  Use the diagram to find the restrictions on clock skew for the double-latch circuit.

    Note that the edge-triggered restrictions was given in class. They were:-
      tCLK > tCHQV + tpd(max) + tSETUP           and           tCHQV  + tpd(min) > tHOLD.
If the clock has skew, this must be included:-
      tCLK > tCHQV + tpd(max) + tSETUP + tSKEW          and           tCHQV + tpd(min) > tHOLD + tSKEW
The first equation is the one used when checking for setup time violations.
The  second equation is used for checking hold times and is important only in shift registers.
 For  tHOLD=0 = tpd(min)  one gets the commonly used skew restriction
     tCHQV >  tSKEW.

What is a similar equation for double-latch circuits?
 

The 6th Assignment (due Tue., Nov. 4 and Tue., Nov 11, 1999)

    Do a  double-latch/dual-edge implementation of the following circuit.  Do a state graph, a Verilog simulation, and synthesis. Show schematics to verify it synthesized into a reasonable circuit.
    A circuit has two synchronous inputs A and B. It has one Moore output Z.
    Starting from an even phase:
            Six or more consecutive zeros or six or more consecutive ones will give Z=1
            If the sequence has less than 6 zeros (ones), the count will not restart on an odd phase, but will wait for the even phase. This means the  1 (0) that broke the sequence  will be part of the next sequence only if it is on an even phase.
    Once Z=1,  it will stay one as long as B=1 noting there is always a one phase delay between inputs and Moore outputs.
    Once B goes low, Z will drop unless the first condition is satisfied.

    Example:     A -> 00,00,00,00,01,11, 11,11,10,11,11,11,11,00
          B -> 11,00,10,00,01,10, 00,00,01,11,11,11,00,01
          Z -> 00,00,00,11,11,11, 00,00,11,11,11,11,11,10

  First part:  Do a state graph and expand it to eliminate odd length loops. It is suggested that you partition the B input into a parallel machine with a much smaller state graph.  This is to save drawing another fifteen  circles almost identical to the first ones. In this case it should not even cause an extra input into the state table.
    Do a state table and a state assignment. Count the number of latches you will need for each phase.
    Code a dual-edge triggered flip-flop in Verilog. Pass in your code only, just state on the bottom if the simulation worked. I will believe you until next week.

    Second part:  Code your machine in Verilog.  Use a synchronous test bench. This means your data will probably be stored in an array.
        Example:
                     @(clock)
                               Tindex=Tindex+1;
                          #1 A = Adata[Tindex];

    After your simulation works, run the same modules (less the test bench) through Synopsis.
(a) Check the latch count against what it should be.

(b) Print out a schematic of the circuit.
(c) Did Synopsys put in latch output MUXs where the same logic was used on both the odd and even phase? In other words did it convert double-latch circuits to dual-edge-triggered flip-flops.?  Try to identify a place where it could have  and did, or could have and did not.  This may depend on how long a clock cycle you allow.
 

7th Assignment (Due Thur. Nov 25)

    Handwritten on a sheet of paper. Three problems.

8th  Assignment Trial Exam (Due, Optional)

Bug reports in the notes etc.

1. In "AUTOMATIC SYNTHESIS DESIGN FLOW USING VERILOG HDL, SYNOPSYS AND CADENCE-XL"
Section III Paragraph 6 should read:
From the Unix prompt, in the directory containing your design, type:
verilog aprog1.v aprog1.tst

 

 
 
 
 
 
 
 

2. In "Introduction to Verilog" by Peter M. Nyasulu & John Knight
Page 25, Example 14.4, line 6 should read:

Q <= {Q[2:0], Q[3]^Q[2]}; /* The concatenation operator ...

 

 
 
 
 
 
 
 

3. In "AUTOMATIC SYNTHESIS DESIGN FLOW USING VERILOG HDL, SYNOPSYS AND CADENCE-XL"
Page 6, in "aprog1.v," change the variable "z" to "zz". as shown below.

// #5 is 5 ns delay.
assign #5 zz = cc | a[0];

The downloadable file "aprog1.v" above was always correct.
Also, if you are using Silos, comment out the $shm instructions in aprog1.tst.

4. Dual-Edge-Triggered Circuits, (Double-Latch p. 4) The transmission gate implementation has the transmission gate control connections
reversed on the two lowest of the six gates.

Documents Distributed in Class

  1. Course outline.
  2. Prerequisite test.
  3. "AUTOMATIC SYNTHESIS DESIGN FLOW USING VERILOG HDL, SYNOPSYS AND CADENCE-XL"

    4. including listings of aprog1.v and aprog1.tst.
  4. "Introduction to Verilog" by Peter M. Nyasulu & John Knight
  5. Copies of "Verilog for Synthesis" overheads, in two installments.
  6. Set of notes on generalized CMOS gate construction, some overheads, some handwritten.
  7. "Making Asynchronous Signals Acceptable in Synchronous Circuit" pp. 1-26
  8. "Races, Cycles in Asynchronous Circuits," pp. 1-35
  9. "Glitches and Hazard's in Digital Circuits," pp.1-16,  17-20, 44-49,
  10. Metastability, pp. 1-33, 34-46.
  11. Clocking for Synchronous FSMs p-6 to p-13 (Hand written)
  12. Double-Clocked Logic, p. 1 - 8.  (Hand written)
  13. One sheet "Asynch Data Stream Proble."  This was a partial solution to assignment 3 and a starting point for assignment 5.
  14. Two pages of updates for Double Clocked Logic. One on "Number of Latches."  One on "Problems With Double Latches."
  15. Three pages on "Dual-Edge-Triggered Circuits." Three slides and three pages of comments on the slides.
  16. Handwritten notes on "Production testing of digital circuits".in general.
  17. Handwritten notes on "Faults and fault models, "starting with a barrel shifter.
  18. Handwritten notes on CMOS fault models (not covered in lecture except briefly).
  19. Handwritten notes on scan testing.
  20. 44 pages of rewritten nots on alternate-latch circuits.
  21. A trial examination.
  22. Notes on boundry scan.