Verilog
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General concepts, overview.
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Verilog for synthesis.
Digital Circuits
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Two-level, multiple-level combinational,
Niche methods (Arrays for discrete logic,
MUX for FPGAs, random logic for ASICs).
Sequential Circuits.
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Conventional clocking.
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Synchronous timing restraints, clock skew,
conventional timing verification,
static timing verification, and false paths.
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Asynchronous inputs, handshaking,
Gray codes, metastability, and arbiters.
Design Methods
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Multiple clocks, alternate-edge clocking.
One-hot, shift-register and data-path circuits.
Clock Distribution
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clock skew.
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distribution methods
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self-timing circuits.
Low Power Circuits
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CV2F, effects of voltage on power and speed.
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Circuit power reduction, such as glitch reduction, and sign-extension elimination.
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Clock power reduction, gating, special f-f.
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Review of functional circuits. A critical look at area, power, latency, and throughput
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Counters; Gray code, ripple, LFSR.
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Addition: parallel, attacks on the carry prob-
lem. Bit-serial, trade power for time (maybe).
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Multiplication
A few traditional schemes
Finite-field arithmetic; multiply as fast as
addition.
Testing
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Defects, fault models
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Combinational test-pattern generation
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Scan, pattial scan
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Built-In Self Test
Logic verification
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binary-decision diagrams
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2-level combinational minimization
High-level synthesis
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operator, storage and interconnect reduction.
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speed and power reduction
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retiming
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heuristic and random optimization.
Dynamic Logic
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Gates; latches and flip-flops.
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