Graduate Course in Electronic Engineering

September 9, 1999 3:33 pm

General:

• The course will deal with digital-circuit design in a world where much logic design is done with synthesis tools. It will review some common digital circuits and design techniques with an emphasis on when one should use them. It will give an overview of low-level and high-level synthesis techniques to try and show their limitations. Then it will look at some current topics like low-power and clock distribution, and testability. The course will uses Verilog for many of the problems and examples but the course is on design, not Verilog syntax, and only a few formal lectures on Verilog will be given. Students will have access to Synopsys and Verilog XL.

Course Content:

• The approximate selection of topics is given below

Verilog General concepts, overview. Verilog for synthesis. Digital Circuits Two-level, multiple-level combinational, Niche methods (Arrays for discrete logic, MUX for FPGAs, random logic for ASICs). Sequential Circuits. Conventional clocking. Synchronous timing restraints, clock skew, conventional timing verification, static timing verification, and false paths. Asynchronous inputs, handshaking, Gray codes, metastability, and arbiters. Design Methods Multiple clocks, alternate-edge clocking. One-hot, shift-register and data-path circuits. Clock Distribution clock skew. distribution methods self-timing circuits. Low Power Circuits CV2F, effects of voltage on power and speed. Circuit power reduction, such as glitch reduction, and sign-extension elimination. Clock power reduction, gating, special f-f.

Adiabatic circuits. Review of functional circuits. A critical look at area, power, latency, and throughput Counters; Gray code, ripple, LFSR. Addition: parallel, attacks on the carry prob- lem. Bit-serial, trade power for time (maybe). Multiplication A few traditional schemes Finite-field arithmetic; multiply as fast as addition. Testing Defects, fault models Combinational test-pattern generation Scan, pattial scan Built-In Self Test Logic verification binary-decision diagrams 2-level combinational minimization High-level synthesis operator, storage and interconnect reduction. speed and power reduction retiming heuristic and random optimization. Dynamic Logic Gates; latches and flip-flops.

Evaluation:

• A number of assignments, typically four, plus a final examination.

Reference Texts:

• Chandrakasan and Broderson, Low Power Digital CMOS Design, Kluwer Academic, 1995, TK7871.99.M44C43
  de Mitcheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994, TK7874.65.D4
  Rabaey, Digital Integrated Circuits, Prentice Hall, 1996.
  M.Smith, Application-Specific Integrated Circuits, Addison-Wesley, 1997.

Other Information:

• John Knight, Associate Prof., Electronics Department. jknight@doe.carleton (works), 613-520-5764 (maybe)
  Course times: Tue. and Thur., 19:30 to 21:00, Sept. 7 to Dec. 2 inclusive; room 3174, Mackenzie Engineering
  Initial organizational meeting, Sept. 7.
  Registration information: call Peggy or Betty at 613-520-5754.