John Knight, Ph.D. (Toronto)

Pic of half-bald prof        

Email:      jknight (at the domain)  doe.carleton.ca
Voice:       (613) 520-5764
FAX:        (613) 520-5708
Office:      5144ME 



Is he likely to be in his office?

Course Notes

    Getting a copy of a .pdf Reader to read course notes.
            http://www.foxitsoftware.com/downloads/
           

ELEC 2607, Switching Circuits

    This is the beginning digital course for Electrical/Systems Engineering students at Carleton.
   The course web page for Winter 2011.  
    This page is a draft and anything on it may change before January.        Direct link to course notes


ELEC 4906,  Electrical Power Engineering ( Taught by Carl Kroop)

     Web page for Winter 2008
     The TA's, Dritan Celo's, web page from Fall 2007

 

97.583,  Digital Circuit Design and Synthesis

     The '583 course description told potential students what to expect as much as one page can. This was last given in the fall of 1999. 

    Problems, corrections, programs for 97.583 are found in  97.583/Notes99.html.
 


Bridge Camp

2003:  There will be no Bridge Camp in 2003, or 2004
2002: This Bridge Camp was sponsored by  Vittesse Reskilling Canada Inc. Details can be seen at   http://www.vitesse.ca/programs/microelectronics.asp.
2001: John regrets that due to unfortunate circumstances (falling off a roof) he was unable to organize a Carleton camp.
2000: The SMC Bridge Camp was two connected two-week courses to bring recent EE graduates up to speed (well almost up to speed) in VLSI design. It was run at Carleton and McGill during June 2000.
1999: This SMC Bridge Camp is described here.

    Note:  On Jan. 1, 2002, the Strategic Microelectronics Consortium (SMC) joined the Information Technology Association of Canada to form the Strategic  Microelectronics CouncilCMC was also heavily involved in these early Camps.

Research Areas

Prof Knight graduated his last Ph.D. student in June 2009, and is not taking any more graduate students.

 

Digital circuits and digital architectures: in particular, the automatic design of digital circuits. This interest includes most aspects of the design, power consumption, including clocking, testing and testability, area minimization/regularization and reliability. Computer-aided design of integrated circuts: the main interest here is high-level (behavioural) synthesis from an algorithm.  A good demonstration is the "Power profiler" from Raul San Martin's thesis.  

Publications

"Physical Resource Binding for a Coarse Grain Reconfigurable Array Using Evolutionary Algorithms,"
    Shing-Fat F. Ma, J. P. Knight and  C Plett,   IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, vol 13, No. 5, May 2005, 11 pages.

·         "Digitally Place and Routed Up-converting Bandpass DAC," Gordon Allan, John Knight, Norman M. Filiol, Tom A. D. Riley:  CCECE 2006: pp. 705-708;  Proc Can Conf on Electrical and Computer Engineering, May 7, 10, 2006,Ottawa, Canada.

·         "A compact 190µW PLL for clock control and distribution in ultra-large scale ICs. ,"Gordon Allan, John Knight: ISCAS 2006, Intl Symp Circuits and Systems, 21-24 May 2006, Is. of Kos, Greece   

·          "Mixed-signal thermometer filtering for low-complexity PLLs/DLLs.," Gordon Allan, John Knight: ISCAS 2006   Intl Symp Circuits and Systems, 21-24 May 2006, Is of Kos, Greece.

·          "Novel Architecture for Ultra Low Complexity Mixed-Signal DLLs," Gordon Alan and John Knight,  2004, Analog VLSI Workshop in Macau, China, Oct 13-15, 2004..

·         "Low Complexity Digital PLL for Instant Acquisition Clock Data Recovery," Gord. Allan and J. Knight,  IEEE ISCAS. Vancouver B.C., May 23-26, 2004.

·         "Physical resource binding for a coarse grain reconfigurable array,” F. Ma, J. P. Knight, and C. Plett, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, vol. ERSA'04,  pp 109-115, June 21-24, 2004, Las Vegas, Nevada

·         “Compatible Cell Connections for Multifamily Dynamic-Logic Gates,” Rolando Ramirez Oriz and J.P. Knight,
     IEEE Trans VLSI, vol. 10, No. 10, June. 2002, pp. 327-340.

·         "Reconfigurable Logic Design Case: FFT on Chameleon",  F. Ma, J. P. Knight and  C Plett,
 Proceedings of SPIE Reconfigurable Technology: FPGAs and Reconfigurable Processors for  Computing and Communications IV,  Boston Mass., pp. 113-117  , July 30 2002

·         “Multi-Clock Selection and Synthesis for CDFGs  using Optimal Clock Sets and Genetic Algorithms,” Elie Torby and J.P.Knight,
  IEEE Trans VLSI,  vol 9, #5,  Oct 2001, pp. 590-607.

·         “Performing Scheduling and Storage Optimization Simultaneously Using Genetic Algorithms,” E. Torbey and J. Knight,
     Midwest Symp. CAS, South Bend, IN, August 1998, pp. 284-287.

·          “Implementation and Trade-offs of a DCT Architecture Using High-Level Synthesis,” E. Torby and J.Knight,
     IEEE International ASIC Conference, 13-16 September 1998 in Rochester, New York, pp. 193-197

·         “Performing scheduling and storage optimization simultaneously using genetic algorithm,” E. Torby and J.P.Knight,
     Midwest Symposium on Circuits and Systems, Notre Dame IN, Aug 10-12, 1998.

·          “A Novel Spacial Technique for Complexity Estimation in Synthesis,”  E. Torby and J.P.Knight,
     IEEE International Logic Workshop
, Lake Tahoe, Calif., June 1998.

·          “High-Level Synthesis of Digital Circuits Using Genetic Algorithms,” E. Torby and J.P.Knight,
     IEEE International Conference on Evolutionary Computing, pp. 224-229, Ancorage Alaska, May 4-9, 1998.

·          “Power Optimization in the Behavioural Synthesis of ASICS,” R. San Martin and J.P. Knight,
     IEEE Design and Test, vol. 13, No. 2, pp. 58-79 1996.

·          “Using Spice and Behavioral Synthesis Tools to Optimize ASICs Peak Power Consumption,” R. San Martin, J. P. Knight,
     38th Midwest Symposium on Circuits and Systems, Rio de Janeiro, 1995

·          “Area/Power/speed Optimization by Mixing Serial/Parallel Operators Using Genetic Algorithms,” R. San Martin and J.P. Knight,
     The Design Automation Conference, San Francisco, June 12-16, 1995.

·         “PASSOS: A Different Approach for Assignment and Scheduling for Power, Area and Speed Optimization in High-Level Synthesis,”
     R. San Martin and J.P. Knight, Proc 37 Midwest Symp. on Circuits and Systems, Lafayette LA., Aug. 3-4, 1994.

·          “Concurrent Testing in High Level Synthesis,” R.Singh and J.P.Knight,
     Proc. of the 7th Inter Symp on High-Level Synthesis, Niagara on the Lake, May 18-20, 1994.

·         “Using Probabilistic Weights for Operator Assignment in Behavioral Synthesis,” R. Shum and J. Knight,
     Proc. Canadian Conference on VLSI, Banff, Alberta., Nov 15-16, 1993.

·         “Genetic Algorithms for the Optimization of Integrated Circuit Synthesis,” R. San Martin and J.P. Knight,
     Proc. of the 5th Int. Conf. on Genetic Algorithms, Urbana Il., July, 1993.

·         "Operations Research in the High-Level Synthesis of Integrated Circuits,"
Computers and Operations Research
, 17, 1993.  R. San Martin and J. Knight

·         "An Address Bit-Shifting Microcontroller for ASICs,"
    Proceedings, Canadian Conference on VLSI
, Halifax, October 1992. T.Q. Lee and J. Knight

·         "Concurrent Testing of Digital ASICs Synthesized from Data-Flow Graphs,"
    Proceedings, 6th Workshop on New Directions in Testing
, Montreal, May 1992. R. Singh, J. Knight and M. Townsend