SPICE Instructions

SPICE 1 MODIFIED USER'S GUIDE

Edited by C. Plett

Department of Electronics, Carleton University

Original by

A. Vladimerescu, A.R. Newton, D.O. Pederson

Department of Electrical Engineering and Computing Science

University of California, Berkely, CA

Longer SPICE Users Guide (from Berkeley)

SPICE is a general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and linear ac analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, transmission lines, and the four most common semiconductor devices: diodes, BJT's, JFET's, and MOSFET's. This manual is a subset of the complete manual and covers items specific to CMOS design.

Three MOSFET models are implemented in SPICE: MOS1 is described by a square-law I-V characteristic, MOS2 is an analytical model, while MOS3 is a semi-empirical model. Both MOS2 and MOS3 include second-order effects such as channel length modulation, subthreshold conduction, scattering limited velocity saturation, small-size effects and charge-controlled capacitances.

Table of Contents

1. TYPES OF ANALYSIS

      1.1.    DC Analysis                
      1.2.    AC Small Signal Analysis
      1.3.    Transient Analysis                                 1
      1.4.    Analysis at Different Temperatures                 2

2. CONVERGENCE

3. INPUT FORMAT

4. CIRCUIT DESCRIPTION

5. TITLE LINE COMMENT AND END

      5.1.    Title                                              3
      5.2.    END Line                                           3
      5.3.    Comments                                           3

6. ELEMENTS

      6.1.    Resistors                                          3
      6.2.    Capacitors and Inductors                           3
      6.3.    Independent Sources                                4
      6.3.1.  Pulse PULSE(V1 V2 TD TR TF PW PER)                 4

7. SEMICONDUCTOR DEVICES

      7.1.    MOSFET'S                                           5
      7.2.    MODEL                                              5
      7.3.    MOSFET Models both N and P Channel                 5

8. CONTROL LINES

      8.1     .DC Card                                           6
      8.2.    .NODESET                                           7
      8.3.    IC                                                 7
      8.4.    TRAN                                               7
      8.5     .AC CARD                                           7
      8.6.    PRINT                                              8
      8.7.    PLOT                                               8

9. APPENDIX A EXAMPLE DATA FILES

      9.1     Circuit 1                                          8
      9.2.    Circuit 2                                          8
      9.3.    Circuit 3                                          9

1. TYPES OF ANALYSIS Back to Table of Contents

1.1. DC Analysis

The dc analysis portion of SPICE determines the dc operating point of the circuit with inductors shorted and capacitors opened. A dc analysis is automatically performed prior to a transient analysis to determine the transient initial conditions.

1.2. AC Small Signal Analysis The ac small-signal portion of SPICE computes the ac output variables as a function of frequency. The program first computes the dc operating point of the circuit and determines linearized, small-signal models for all of the nonlinear devices in the circuit. The resultant linear circuit is then analyzed over a user-specified range of frequencies. The desired output of an ac small- signal analysis is usually a transfer function (voltage gain, transimpedance, etc). If the circuit has only one ac input, it is convenient to set that input to unity and zero phase, so that output variables have the same value as the transfer function of the output variable with respect to the input.

1.3. Transient Analysis

The transient analysis portion of SPICE computes the transient output variables as a function of time over a user-specified interval. The initial conditions are automatically determined by a dc analysis. All sources which are not time dependent (for example, power supplies) are set to their dc value.

1.4. Analysis at Different Temperatures

All input data for SPICE is assumed to have been measured at 27 deg C (300 deg K). The simulation also assumes a nominal temperature of 27 deg C. The circuit can be simulated at other temperatures by using a .TEMP control line.

Temperature appears explicitly in the value of surface mobility, UO, for the MOSFET model. The temperature dependence is determined by:

UO(TEMP) = UP(TNOM)/(TEMP/TNOM)**(1.5)

The effects of temperature on resistors is modeled by the formula:

value(TEMP) = value(TNOM)*(1+TC1*(TEMP-TNOM)+TC2*(TEMP-TNOM)**2)

where TEMP is the circuit temperature, TNOM is the nominal temperature, and TC1 and TC2 are the first- and second-order temperature coefficients.

2. CONVERGENCE Back to Table of Contents

Both dc and transient solutions are obtained by an iterative process which is terminated when both of the following conditions hold:

      1.      The nonlinear branch currents converge to within a 
              tolerance of 0.1 percent or 1 picoamp (1.0E-12 Amp), 
              whichever is larger.

      2.      The node voltages converge to within a tolerance 
              of 0.1 percent or 1 microvolt (1.0E-6 Volt), whichever 
              is larger.

Although the algorithm used in SPICE has been found to be very reliable, in some cases it will fail to converge to a solution. When this failure occurs, the program will print the node voltages at the last iteration and terminate the job. In such cases, the node voltages that are printed are not necessarily correct or even close to the correct solution.

3. INPUT FORMAT Back to Table of Contents

The input format for SPICE is one of the free format type. Fields on an input file are separated by one or more blanks, a comma, an equal (=) sign, or a left or right parenthesis; extra spaces are ignored. A line may be continued by entering a + (plus) in column 1 of the following line; SPICE continues reading beginning with column 2.

A name field must begin with a letter (A through Z) and cannot contain any delimiters. Only the first eight characters of the name are used.

A number field may be an integer field (12, -44), a floating point field (3.14159), either an integer or floating point number followed by an integer exponent (1E-14, 2.65E3), or either an integer or a floating point number followed by one of the following scale factors:

              T=1E12   G=1E9       MEG=1E6     K=1E3      MIL=25.4E-6
              M=1E-3   U=1E-6      N=1E-9      P=1E-12    F=1E-15

Letters immediately following a number that are not scale factors are ignored, and letters immediately following a scale factor are ignored. Hence, 10, 10V 10VOLTS, and 10HZ all represent the same number, and M, MA, MSEC, and MMHOS all represent the same scale factor. Note that 1000, 1000.0, 1000HZ, 1E3, 1.0E3, 1KHZ and 1K all represent the same number.

4. CIRCUIT DESCRIPTION Back to Table of Contents

The circuit to be analyzed is described to SPICE by a set of element lines, which define the circuit topology and element values, and a set of control lines, which define the model parameters and the run controls. The first line in the input file must be a title, and the last line must be ".END". The order of the remaining lines is arbitrary (except, of course, that continuation lines must immediately follow the line being continued.

Each element in the circuit is specified by an element line that contains the element name, the circuit nodes to which the element is connected, and the values of the parameters that determine the electrical characteristics of the element. The first letter of the element name specifies the element type. The format for the SPICE element types is given in what follows. The strings XXXXXXX, YYYYYYY and ZZZZZZZ denote arbitrary alphanumeric strings. For example, a resistor name must begin with the letter R and can contain from one to eight characters. Hence, R, R1, RSE, ROUT, and R3AC2ZY are valid resistor names.

Data fields that are enclosed in lt and gt signs '{}' are optional. All indicted punctuation (parentheses, equal signs, etc.) are required. With respect to branch voltages and currents, SPICE uniformly uses the associated reference convention (current flows in the direction of voltage drop).

Nodes must be non-negative integers but need not be numbered sequentially. The datum (ground) node must be numbered zero. The circuit cannot contain a loop of voltage sources and/or inductors and cannot contain a cutset of current sources and/or capacitors. Each node in the circuit must have a dc path to ground. Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections anyway)

5. TITLE LINE COMMENT AND END Back to Table of Contents

5.1. Title

Examples

       POWER AMPLIFIER CIRCUIT
       TEST OF CAM CELL

This card must be the first line in the input file. Its contents are printed verbatim as the heading for each section of output.

5.2. END Line

Examples

       .END

This must always be the last line in the input file. Note that the period is an integral part of the name.

5.3. Comments

General Form

       * {any comment}

Examples

       * RF=1K    GAIN SHOULD BE 100
       * MAY THE FORCE BE WITH MY CIRCUIT

The asterisk in the first column indicates that this is a comment. Comments may be placed anywhere in the circuit description.

6. ELEMENTS Back to Table of Contents

6.1. Resistors

General form

      RXXXXXXX N1 N2 VALUE {TC=TC1{,TC2}}

Examples

      R1 1 2 100
      RC1 12 17 1K TC=0.0001,0.015

N1 and N2 are the two element nodes. VALUE is the resistance (in ohms) and may be positive or negative but not zero. TC1 and TC2 are the (optional) temperature coefficients; if not specified, zero is assumed for both. The value of the resistor as a function of temperature is given by:

value(TEMP) = value(TNOM)*(1+TC1*(TEMP-TNOM)+TC2*(TEMP-TNOM)**2)

6.2. Capacitors and Inductors

General form

      CXXXXXXX N+ N- VALUE 
      LYYYYYYY N+ N- VALUE 

Examples

      CBYP 13 0 1UF
      COSC 17 13 1OU IC=3V
      LLINK 42 69 1UH
      LSHUNT 23 51 1OU IC=15.7MA

N+ and N- are the positive and negative nodes, respectively. VALUE is the capacitance in Farads or the inductance in Henries.

For the capacitor, the (optional) initial condition is the initial (time- zero) value of capacitor voltage (in Volts). For the inductor, the (optional) initial condition is the initial (time-zero) value of inductor current (in Amps) that flows from N+, through the inductor, to N-. Note that the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN line.

Nonlinear capacitor and inductors can be described.

General form

      CXXXXXXX N+ N- POLY C0 C1 C2 ... 
      LYYYYYYY N+ N- POLY L0 L1 L2 ... 

CO C1 C2 ... (and L0 L1 L2 ...) are the coefficients of a polynomial describing the element value. The capacitance is expressed as a function of the voltage across the element while the inductance is a function of the current through the inductor. The value is computed as:

      value=C0+C1*V+C2*V**2+...
      value=L0+L1*I+L2*I**2+...

where V is the voltage across the capacitor and I the current flowing in the inductor.

6.3. Independent Sources

General form

      VXXXXXXX N+ N- {{DC} DC/TRAN VALUE} {AC {ACMAG {ACPHASE}}}
      IYYYYYYY N+ N- {{DC} DC/TRAN VALUE} {AC {ACMAG {ACPHASE}}}

Examples

      VCC 10 0 DC 6
      VIN 13 2 0.0001 AC 1 SIN(0 1 1MEG)
      ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K)
      VMEAS 12 9

N+ and N- are the positive and negative nodes, respectively. Note that voltage sources need not be grounded. Positive current is assumed to flow from the positive node, through the source, to the negative node. A current source of positive value will force current to flow out of the N+ node, through the source, and into the N- node. Voltage sources, in addition to being used for circuit excitation, are the 'ammeters' for SPICE; that is, zero valued voltage sources may be inserted into the circuit for the purpose of measuring current. They will, of course, have no effect on circuit operation since they represent short-circuits. DC/TRAN is the dc and transient analysis value of the source. If the source value is zero both for dc and transient analyses, this value may be omitted. If the source value is time-invariant (e.g., a power supply), then the value may optionally be preceded by the letters DC.

Any independent source can be assigned a time-dependent value for transient analysis. If a source is assigned a time-dependent value, the time-zero value is used for dc analysis. There are five independent source functions: pulse, exponential, sinusoidal, piece-wise linear, and single-frequency FM. If parameters other than source values are omitted or set to zero, the default values shown will be assumed. (TSTEP is the printing increment and TSTOP is the final time (see .TRAN for explanation).)

6.3.1. Pulse PULSE(V1 V2 TD TR TF PW PER)

Examples

      VIN 3 0 PULSE(-1 1 2NS 2NS 2NS 50NS 100NS)

      parameters               default values            units

      V1 (initial value)                            Volts or Amps
      V2 (pulsed value)                             Volts or Amps
      TD (delay time)              0.0                 seconds
      TR (rise time)               TSTEP               seconds
      TF (fall time)               TSTEP               seconds
      PW (pulse width)             TSTOP               seconds
      PER (period)                 TSTOP               seconds

A single pulse so specified is described by the following table:

                       time              value

                       0                 V1
                       TD                V1
                       TD+TR             V2
                       TD+TR+PW          V2
                       TD+TR+PW+TF V1
                       TSTOP             V1

Intermediate points are determined by linear interpolation.

7. SEMICONDUCTOR DEVICES Back to Table of Contents

The elements that have been described to this point typically require only a few parameter values to specify completely the electrical characteristics of the element. However, the models for the four semiconductor devices that are included in the SPICE program require many parameter values. Moreover, many devices in a circuit often are defined by the same set of device model parameters. For these reasons, a set of device model parameters is defined on a separate .MODEL line and assigned a unique model name. The device element lines in SPICE then reference the model name. This scheme alleviates the need to specify all of the model parameters on each device element line.

Each device element line contains the device name, the nodes to which the device is connected, and the device model name. In addition, other optional parameters may be specified for each device: geometric factors and an initial condition.

The area factor used on the diode, BJT and JFET device card determines the number of equivalent parallel devices of a specified model. The affected parameters are marked with an asterisk under the heading 'area' in the model descriptions below. Several geometric factors associated with the channel and the drain and source diffusions can be specified on the MOSFET device card.

Two different forms of initial conditions may be specified for devices. The first form is included to improve the dc convergence for circuits that contain more than one stable state. If a device is specified OFF, the dc operating point is determined with the terminal voltages for the device set to zero. After convergence is obtained, the program continues to iterate to obtain the exact value for the terminal voltages. If a circuit has more than one dc stable state, the OFF option can be used to force the solution to correspond to a desired state. If a device is specified OFF when in reality the device is conducting, the program will still obtain the correct solution (assuming the solutions converge) but more iterations will be required since the program must independently converge to two separate solutions. .NODESET serves a similar purpose as the OFF option. The .NODESET option is easier to apply and is the preferred means to aid convergence.

The second form of initial conditions are specified for use with the transient analysis. These are true 'initial conditions' as opposed to the convergence aids above. See the description of .IC and .TRAN for a detailed explanation of initial conditions.

7.1. MOSFET's

General form

      MXXXXXXX ND NG NS NB MNAME {L=VAL} {W=VAL} {AD=VAL} {AS=VAL}
      + {PD=VAL} {PS=VAL} {NRD=VAL} {NRS=VAL} {OFF} {IC=VDS,VGS,VBS}

Examples

      M1 24 2 0 20 TYPE1
      M31 2 17 6 10 MODM L=5U W=2U
      M31 2 16 6 10 MODM 5U 2U
      M1 2 9 3 0 MOD1 L=10U W=5U AD=100P AS=100P PD=40U PS=40U
      M1 2 9 3 0 MOD1 1OU 5U 2P 2P

ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively. MNAME is the model name. L and W are the channel length and width, in meters. AD and AS are the areas of the drain and source diffusions, in sq-meters. Note that the suffix U specifies microns (1E-6 m) and P sq-microns (1E-12 sq-m). If any of L, W, AD, or AS are not specified, default values are used. The user may specify the values to be used for these default parameters, with .OPTIONS. The use of defaults simplifies input file preparation, as well as the editing required if device geometries are to be changed. PD and PS are the perimeters of the drain and source junctions, in meters. NRD and NRS designate the equivalent number of squares of the drain and source diffusions; these values multiply the sheet resistance RSH specified on .MODEL for an accurate representation of the parasitic series drain and source resistance of each transistor. PD and PS default to 0.0, while NRD and NRS default to 1.0. OFF indicates an (optional) initial condition specification using IC=VDS,VGS,VBS is intended for use with the UIC option on the .TRAN line, when a transient analysis is desired starting from other than the quiescent operating point. See .IC for a better and more convenient way to specify transient initial conditions.

7.2. MODEL

General form

      .MODEL MNAME TYPE(PNAME1=PVAL1 PNAME2=PVAL2 ... )

Examples

      .MODEL MOD1 NPN BF=50 IS=1E-13 VBF=50

.MODEL specifies a set of model parameters that will be used by one or more devices. MNAME is the model name, and type one of the following seven types:

              NPN      NPN BJT model
              PNP      PNP BJT model
              D        diode model
              NJF      N-channel JFET model
              PJF      P-channel JFET model
              NMOS     N-channel MOSFET model
              PMOS     P-channel MOSFET model

Parameter values are defined by appending the parameter name, as given below for each model type, followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type.

7.3. MOSFET Models both N and P Channel

Spice provides three MOSFET device models which differ in the formulation of the I-V characteristic. The variable LEVEL specifies the model to be used:

      LEVEL=1 -}  Shichman-Hodges
      LEVEL=2 -}  MOS2 (as described in ?1?)
      LEVEL=3 -}  MOS3, a semi-empirical model (see ?1?)

The dc characteristics of the MOSFET are defined by the device parameters VTP, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ... ) are given, but user-specified values always override. VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is modeled by three constant capacitors, CGSO, CGDO and CGBO which represent overlap capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source, drain, and bulk regions using charge conservation, and by the nonlinear depletion-layer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MF and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. The sharing of the channel charge between drain and source in the saturation region is determined by the parameter XQC.

There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m**2). Whereas the first is an absolute value, the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device line; the areas can be defaulted. The same idea applies also to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m**2) on the other. The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device card.

      name    parameter                              units      default

 1    LEVEL   model index                             -          1
 2    VTO     zero-bias threshold voltage             V          0.0
 3    KP      transconductance parameter              A/V**2     2.0E-
 4    GAMMA   bulk threshold parameter                V**0.5     0.0
 5    PHI     surface potential                       V          0.6
 6    LAMBDA  channel-length modulation
              (MOS1 and MOS2 only)                    1/V        0.0
 7    RD      drain ohmic resistance                  Ohm        0.0
 8    RS      source ohmic resistance                 Ohm        0.0
 9    CBD     zero-bias B-D junction capacitance      F          0.0
10    CBS     zero-bias B-S junction capacitance      F          0.0
11    IS      bulk junction saturation current        A          1.0E-14
12    PB      bulk junction potential                 V          0.8
13    CGSO    gate-source overlap capacitance
              per meter channel width                 F/m        0.0
14    CGDO    gate-drain overlap capacitance
              per meter channel width                 F/m        0.0
15    CGBO    gate-bulk overlap capacitance
              per meter channel length                F/m        0.0
16    RSH     drain and source diffusion
              sheet resistance                        Ohm/sq.    0.0
17    CJ      zero-bias bulk junction bottom cap.
              per sq-meter of junction area           F/m**2     0.0
18    MJ      bulk junction bottom grading coef.        -        0.5
19    CJSW    zero-bias bulk junction sidewall cap.
              per meter of junction perimeter         F/m        0.0
20    MJSW    bulk junction sidewall grading coef.      -        0.33
21    JS      bulk junction saturation current
              per sq-meter of junction area           A/m**2     1.0E-8
22    TOX     oxide thickness                         meter      1.0E-7
23    NSUB    substrate doping                        1/cm**3    0.0
24    NSS     surface state density                   1/cm**2    0.0
25    NFS     fast surface state density              1/cm**2    0.0
26    TPG     type of gate material                   -          1.0
                  +1 opp. to substrate
                  -1 same as substrate
                   0 Al gate
27    XJ      metallurgical junction depth            meter      0.0
28    LD      lateral diffusion                       meter      0.0
29    UO      surface mobility                        cm**2/V-s  600
30    UCRIT   critical field for mobility
              degradation (MOS2 only)                 V/cm       1.0E4
31    UEXP    critical field exponent in
              mobility degradation (MOS2 only)        -          0.0
32    UTRA    transverse field coef (mobility)
              (MOS2 only)                             -          0.0
33    VMAX    maximum drift velocity of carriers      m/s        0.0
34    NEFF    total channel charge (fixed and mobile)
              coefficient (MOS2 only)                 -          1.0
35    XQC     coefficient of channel charge
              share attributed to drain               -          0.0
36    KF      flicker noise coefficient               -          0.0
37    AF      flicker noise exponent                  -          1.0
38    FC      coefficient for forward-bias
              depletion capacitance formula           -          0.5
39    DELTA   width effect on threshold voltage
              (MOS2 and MOS3)                         -          0.0
40    THETA   mobility modulation (MOS3 only)         1/V        0.0
41    ETA     static feedback (MOS3 only)             -          0.0
42    KAPPA   saturation field factor (MOS3 only)     -          0.2

?1 A. Valdimirescu and S. Liu, "The Simulation of MOS Integrated Circuits Using SPICE2," ERL Memo ~ ERL M80/7, Electronics Research Laboratory, University of California, Berkely, February 1980.

8. CONTROL LINES Back to Table of Contents

8.1. .DC Card

General form

      .DC SRCNAM VSTART VSTOP VINCR [SRC2 START2 STOP2 INCR2]

Examples

      .DC VIN 0.25 5.0 0.25
      .DC VDS 0 10 .5 VGS 0 5 1
      .DC VCE 0 10 .25 IB 0 10U 1U

This card defines the dc transfer curve source and sweep limits. SRCNAM is the name of an independent voltage or current source. VSTART, VSTOP, and VINCR are the starting, final, and incrementing values respectively. The first example will cause the value of the voltage source VIN to be swept from 0.25 Volts to 5.0 Volts in increments of 0.25 Volts. A second source (SRC2) may optionally be specified with associated sweep parameters. In this case, the first source will be swept over its range for each value of the second source. This option can be useful for obtaining semiconductor device output characteristics. See the first example data deck in that section of the guide.

8.2. .NODESET Card

General form

      .NODESET V(NODNUM)=VAL V(NODNUM)=VAL ...

Examples

      .NODESET V(12)=4.5 V(4)=2.23

This card helps the program find the dc or initial transient solution by making a preliminary pass with the specified nodes held to the given voltages. The restriction is then released and the iteration continues to the true solution. The .NODESET card may be necessary for convergence on bistable or astable circuits. In general, this card should not be necessary.

8.3. IC

General form

      .IC V(NODNUM)=VAL V(NODNUM)=VAL ...

Examples

      .IC V(11)=5 V(4)=-5 V(2)=2.2

This is for setting transient initial conditions.

8.4. TRAN

General form

      .TRAN TSTEP TSTOP {TSTART}{TMAX}} {UIC}

Examples

      .TRAN 1NS 100NS
      .TRAN 1NS 1000NS 500ns
      .TRAN 10NS 1US UIC

TSTEP is the printing or plotting increment for line-printer output. For use with the post-processor, TSTEP is the suggested computing increment. TSTOP is the final time, and TSTART is the initial time. If TSTART is omitted, it is assumed to be zero. The transient analysis always begins at time zero. In the interval {zero, TSTART}, the circuit is analyzed (to reach a steady state), but no outputs are stored. In the interval {TSTART, TSTOP}, the circuit is analyzed and outputs are stored. TMAX is the maximum stepsize that SPICE will use (for default, the program chooses either TSTEP or (TSTOP-TSTART)/50.0, whichever is smaller. TMAX is useful when one wishes to guarantee a computing interval which is smaller than the printer increment, TSTEP.

UIC (use initial conditions) is an optional keyword which indicates that the user does not want SPICE to solve for the quiescent operating point before beginning the transient analysis. If this keyword is specified, SPICE uses the values specified using IC=... on the various elements as the initial transient condition and proceeds with the analysis. If .IC has been specified, then the node voltages on .IC are used to compute the initial conditions for the devices. Look at the description on .IC for its interpretation when UIC is not specified.

8.5. .AC CARD

General form

      .AC DEC ND FSTART FSTOP
      .AC OCT NO FSTART FSTOP
      .AC LIN NP FSTART FSTOP

Examples

      .AC DEC 10 1 10K
      .AC DEC 10 1K 100MEG
      .AC LIN 100 1 100HZ

DEC stands for decade variation, and ND is the number of points per decade. OCT stands for octave variation, and NO is the number of points per octave. LIN stands for linear variation, and NP is the number of points. FSTART is the starting frequency, and FSTOP is the final frequency. If this card is included in the deck, SPICE will perform an ac analysis of the circuit over the specified frequency range. Note that in order for this analysis to be meaningful, at least one independent source must have been specified with an ac value.

8.6. PRINT

General form

      .PRINT PRTYPE OV1 

Examples

      .PRINT TRAN V(4) I(VIN)
      .PRINT AC VM(4,2) VR(7) VI(7) 
      .PRINT AC VDB(5) VP(5) IR(7) II(8)
      .PRINT DC V(2) I(VSRC) V(23,17)
      .PRINT NOISE INOISE
      .PRINT DISTO HD3 SIM2(DB)

This defines the contents of a tabular listing of one to eight output variables. PRTYPE is the type of the analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired.

8.7. PLOT

General form

      .PLOT PLTYPE OV1 {(PLO1,PHI1)} {OV2 {(PLO2,PHI2)} ... OV8}

Examples

      .PLOT DC V(4) V(5) V(1)
      .PLOT TRAN V(17,5) (2,5) I(VIN) V(17) (1,9)
      .PLOT AC VM(5) VM(31,24) VDB(5) VP(5)
      .PLOT DISTO HD2 HD3(R) SIM2
      .PLOT TRAN V(5,3) V(4) (0,5) V(7) (0,10)

This defines the contents of one plot of from one to eight output variables. PLTYPE is the type of analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired. The syntax for the OV1 is identical to that for .PRINT, described above.

The optional plot limits (PLO,PHI) may be specified after any of the output variable. All output variables to the left of a pair of plot limits (PLO,PHI) will be plotted using the same lower and upper plot bounds. If plot limits are not specified. SPICE will automatically determine the minimum and maximum values of all output variables being plotted and scale the plot to fit. More than one scale will be used if the output variable values warrant (i.e., mixing output variables with values which are orders-of-magnitude different still gives readable plots).

The overlap of two or more traces on any plot is indicated by the letter X.

When more than one output variable appears on the same plot, the first variable specified will be printed as well as plotted. If a printout of all variables is desired, then a companion .PRINT line should be included.

There is no limit on the number of .PLOT lines specified for each type of analysis.

9. APPENDIX A EXAMPLE DATA FILES Back to Table of Contents

9.1. Circuit 1

The following file computes the output characteristics of a MOSFET device over the range 0-10V for VDS and 0-5V VGS.

      MOS OUTPUT CHARACTERISTICS
      .OPTIONS NODE NOPAGE
      VDS 3 0
      VGS 2 0
      M1 1 2 0 0 MOD1 L=4U W=6U AD=10P AS=10P
      .MODEL MOD1 NMOS VTO=-2 NSUB=1.0E15 UP=550
      * VIDS MEASURES ID, WE COULD HAVE USED VDS, BUT ID WOULD BE NEG
      VIDS 3 1
      .DC VDS 0 10 .5 VGS 0 5 1
      .PRINT DC I(VIDS) V(2)
      .PLOT DC I(VIDS)
      .END

9.2. Circuit 2

The following file determines the dc transfer curve and the transient pulse response of a simple RTL inverter. The input is a pulse from 0 to 5 Volts with delay, rise, and fall times of 2ns and a pulse width of 30ns. The transient interval is 0 to 100ns, with printing to be done every nanosecond.

      SIMPLE RTL INVERTER
      VDD 4 0 5
      VIN 1 0 PULSE 0 5 2NS 2NS 2NS 30NS
      RB 1 2 10K
      Q1 3 2 0 Q1
      RC 3 4 1K
      .PLOT DC V(3)
      .PLOT TRAN V(3) (0,5)
      .PRINT TRAN V(3)
      .MODEL Q1 NPN BF 20 RB 100 TF .1NS CJC 2PF
      .DC VIN 0 5 0.1
      .TRAN 1NS 100NS
      .END

9.3. Circuit 3

The following file simulates a four-bit binary adder, using several subcircuits to describe various pieces of the overall circuit.

      ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER

        *** SUBCIRCUIT DEFINITIONS

      .SUBCKT NAND 1 2 3 4

        * NODES:  INPUT (2), OUTPUT, VCC
      Q1 9 5 1 QMOD
      D1CLAMP 0 1 DMOD
      Q2 9 5 2 QMOD
      D2CLAMP 0 2 DMOD
      RB 4 5 4K
      R1 4 6 1.6K
      Q3 6 9 8 QMOD
      R2 8 0 1K
      RC 4 7 130
      Q4 7 6 10 QMOD
      DVBEDROP 10 3 DMOD
      Q5 3 8 0 QMOD
      .ENDS NAND
      .SUBCKT ONEBIT 1 2 3 4 5 6
        *  NODES:  INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC
      X1 1 2 7 6 NAND
      X2 1 7 8 6 NAND
      X3 2 7 9 6 NAND
      X4 8 9 10 6 NAND
      X5 3 10 11 6 NAND
      X6 3 11 12 6 NAND
      X7 10 11 13 6 NAND
      X8 12 13 4 6 NAND
      X9 11 7 5 6 NAND
      .ENDS ONEBIT
      .SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9
        *  NODES:   INPUT - BIT0(2) / BIT1(2), OUTPUT - BITO / BIT
        *           CARRY-IN, CARRY-OUT, VCC
      X1 1 2 7 5 10 9 ONEBIT
      X2 3 4 10 6 8 9 ONEBIT
      .ENDS TWOBIT

      .SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
        *  NODES:  INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2),
        *          OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, C
      X1 1 2 3 4 9 10 13 16 15 TWOBIT
      X2 5 6 7 8 11 12 16 14 15 TWOBIT
      .ENDS FOURBIT

        *** DEFINE NOMINAL CIRCUIT

      .MODEL DMOD D
      .MODELQMOD NPN(BF=75) RB=100 CJE=1PF CJC=3PF)
      VCC 99 0 DC 5V
      VIN1A 1 0 PULSE(0 3 0 10NS 10NS   10NS   50NS)
      VIN1B 2 0 PULSE(0 3 0 10NS 10NS   20NS  100NS)
      VIN2A 3 0 PULSE(0 3 0 10NS 10NS   40NS  200NS)
      VIN2B 4 0 PULSE(0 3 0 10NS 10NS   80NS  400NS)
      VIN3A 5 0 PULSE(0 3 0 10NS 10NS  160NS  800NS)
      VIN3B 6 0 PULSE(0 3 0 10NS 10NS  320NS 1600NS)
      VIN4A 7 0 PULSE(0 3 0 10NS 10NS  640NS 3200NS)
      VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS)
      X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT
      RBIT0 9 0 1K
      RBIT1 10 0 1K
      RBIT2 11 0 1K
      RBIT3 12 0 1K
      RBIT4 13 0 1K
      RCOUT 13 0 1K
      .PLOT TRAN V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
      .PLOT TRAN V(9) V(10) V(11) V(12) V(13)
      .PRINT TRAN V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8)
      .PRINT TRAN V(9) V(10) V(11) V(12) V(13)

        ***(FOR THOSE WITH MONEY (AND MEMORY) TO BURN)
      .TRAN 1NS 6400NS

      .OPTIONS ACCT LIST NODE LIMPTS=6401
      .END

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(laboriously wordprocessed by D. Piamonte)


Last update September 24, 1997.