Ram Achar, Ph. D, P. Eng. Home›

Fellow IEEE, Fellow EIC

Professor

Department of Electronics, Carleton University
Ottawa, Ontario, Canada - K1S 5B6
Ph: 613-520-2600, Ext 5651; Fax: 613-520-5708
Email: achar@doe.carleton.ca

For more informative contact links, please click here (last updated: Sept. 2022)

Research Interests:

· CAD for VLSI, Design Automation

· Mixed-Domain and Multi-Physics Modeling/Simulation Algorithms

· Parallel Circuit/EM/RF Simulation Algorithms

· Signal and Power Integrity Modeling/Analysis Methods

· Co-Performance Modeling/Analysis for Chip, Package and Systems

· Modeling and Simulation of High-Speed Interconnects

· Model-Order Reduction Techniques

· Design Tools for RF, Wireless, MEMS and Optoelectronic Applications

· Electromagnetic Compatibility (EMC/EMI) analysis of VLSI systems

· Numerical Algorithms

Research Overview

Computer-Aided Design Tools and Methodologies for Modeling/Analysis of High-Speed VLSI Circuits, Packages, Systems and Mixed-Domain Applications

The recent trends toward higher-density, lower-power, higher operating speeds, sharper excitations and more complex designs demand essential changes in the VLSI (Very Large Scale Integration) design/verification methodologies and the associated computer-aided design (CAD) tools. With the increasing signal-speed and decreasing feature sizes, high-speed interconnect effects such as delay, attenuation, reflection, and crosstalk become the dominant factors limiting overall performance of microelectronic systems.

High-speed modules can be diverse, and can exist at any of the hierarchical levels of VLSI systems, including integrated circuits, printed circuit boards, multi-chip modules, packages and backplanes. It is imperative to note that, due to higher frequencies, the traditional and artificial boundaries between different design disciplines such as electrical, thermal and mechanical, etc. are fast vanishing. In addition, due to the current nano-scale processes, process variability and its impact on design performance as well as yield is becoming a major concern. Also, low power requirements are leading to reduced noise margins that are becoming increasingly challenging to achieve.

Consequently, the above trends are warranting seamless integration of chip, package and systems with heterogeneous modules such as MEMS, RF, electromagnetic and optoelectronic blocks etc. along with digital as well as analog blocks. Conventional CAD methods and tools do not handle adequately the new emerging challenges of high-speed circuits, interconnects and mixed-domain problems. However, if not considered during the early design stages, high-speed effects can result in system failure, leading to extra iterations in the design cycle and steeply increased cost.

To cope with these new requirements of managing the complexity of high-speed and mixed-domain modules, coordinated research activities spanning various design domains are proposed with the goal of developing new generation CAD algorithms and tools to facilitate easy, efficient and accurate modeling/analysis/optimization process. The proposed methodologies and algorithms will be suitable for iterative interactive design techniques requiring repetitive analysis of large high-speed systems and are expected to lead to shorter design cycles, reduced time-to-market and better quality high-speed electronic systems.

Awards & Distinctions

Recognizing the strategic importance of the research, it has been awarded by several leading organizations and microelectronic forums:

1. Member of Board of Governors (2023) – IEEE EMCS

Serving as the member of the BoG of the Electromagnetic Compatibility Society.

2. Distinguished Lecturer (since 2020) – IEEE EPS

Selected as the “Distinguished Lecturer”, under the DLP program by the Electronic Packaging Society (EPS) to advance the area of Advanced packaging, High-Speed Interconnects, Signal and Power Integrity.

3. Best Paper Award (EPEPS - 2020)

Received the Best Conference Paper Award for the contribution, "Gauss-Newton Method for Performance Evaluation of Decoupling Capacitors on Resonant Parallel Plates", Proc. 29^th IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct. 2020, San Jose, CA. This work was selected as the best paper of the conference (co-author).

4. Chair, Distinguished Lecturer Program (since 2017) – IEEE EMCS

Serving as the chair of the Distinguished Lecturer Program of the IEEE Electromagnetic Compatibility Society (EMCS). The responsibility in this task includes, soliciting DL speaker nominations, selecting DL speakers, DL talk/travel approvals, administering the DL budget and related interactions with the EMCS chapter chairs worldwide (Since 2017).

5. Distinguished Lecturer (since 2017) – IEEE EDS

Selected as the “Distinguished Lecturer”, under the DLP program by the Electron Devices Society (EDS) to advance the area of nanoscale devices and interconnects and high-speed issues.

6. Distinguished Lecturer (2015, 2016) – IEEE EMCS

Selected as the “Distinguished Lecturer”, under the DLP program by the Electromagnetic Compatibility Society (EMCS) for years 2011 & 2012 to advance the area of signal and power integrity.

7. Fellow, Engineers Institute of Canada (Class of 2015)

Recognized with the "Fellow of Engineers Institute of Canada (EIC)", the highest grade of EIC membership for "Contributions to High-Speed Interconnect Analysis" (2015).

8. Bharat Gaurav Award (2014)

Conferred with the “Bharat Gaurav Award” (India Honor Award) by the India International Friendship Society (IIFS), at the “Global Friendship Day” in New Delhi, India, Jan 2014. The Award is conferred to those individuals who have made outstanding contributions in their specialized fields while also significantly contributing to enhance the relationships between India and their chosen country.

9. Best IEEE Transactions Paper Award (T-CPMT - 2013)

B. Nouri, M. Nakhla, and R. Achar, "Optimum Order Estimation for Reduced Macromodels based on a Geometrical Approach to Model Order Reduction," IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1218-1227, July 2013. This work was selected as the best contributions paper for the year 2013 by the editorial board of IEEE TCPMT (co-author).

10. Fellow, IEEE (Class of 2013)

Recognized with the "Fellow of IEEE", the highest grade of IEEE membership for "Contributions to Interconnects and Signal Integrity Analysis in High-Speed Designs" (2013).

11. Guest Editor (2012, 2013)

Guest Editor for two special issues of IEEE Transactions on Components, Packaging, Manufacturing and Technology (T-CPMT) on "Macromodeling and Variability in Nanoscale Designs" and "3D-ICs and Interconnects".

12. Distinguished Lecturer (2011, 2012) – IEEE CASS

Selected as the “Distinguished Lecturer”, under the DLP program by the Circuits and Systems Society (CASS) for years 2011 & 2012 to advance the area of signal and power integrity.

13. General Chair, HPCPS (2012, 2013)

Founding Member and the General Chair for HPCPS (IEEE International Workshop on High-Performance Chip, Package and Systems: (www.hpcps.org).

14. International Guest Faculty, MCIT-DIT of Govt of India (2011)

Invited by the Ministry of Information Technology and Communications of Government of India (MCIT-DIT). As part of this invitation, he visited (Nov-Dec 2011) and delivered a series of guest lectures focused on VLSI Interconnects and signal integrity at several premier institutes in India, including IISC-Bangalore, IIT--Delhi, IIT-Bombay, IIT-Kharagpur, CEERI-Pilani and BITS-Pilani.

15. Chair, Joint Chapter of CAS/EDS/SSC Societies of the IEEE Ottawa Section (since - 2005)

Chair of the joint chapter of Circuits and Systems Society (CAS), Electronics Devices Society (EDS) and Solid State Circuits Society (SSC) of Ottawa IEEE Section (Chair since 2005).

16. General Co-Chair (EPEPS - 2010, 2011)

Elected as the General Co-Chair for the "IEEE International Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)" for years 2010 (Austin, Texas) & 2011 (San Jose, California). EPEPS is the world’s premier conference focused on signal integrity, power integrity, advanced packaging methodologies and high-speed interconnects. Also served as the chair of the Executive Committee and Technical Program committee of EPEPS.

17. Best Paper Award (SPI - 2011)

Received the Best Conference Paper Award for the contribution, “A Novel Algorithm for Optimum Order Estimation of Reduced Macromodel, 15th IEEE International Workshop on Signal Propagation on Interconnects., pp. IV.4.1-IV.4.2, May 2011, Naples, Italy. This work was selected as the best paper of the conference (co-author).

18. Research Achievement Award (2010)

Recipient of the prestigious Research Achievement Award (RAA) by the Carleton University. Each year Carleton university recognizes five professors for the excellence in their research. Award consists of a certificate and a research grant of $15,000.

19. NSERC Doctoral Medal (2010)

Natlaie Nakhla was awarded the prestigious NSERC doctoral medal for her doctoral work on massively coupled interconnect analysis. Only four such medals are given in a year throughout Canada, among all Canadian universities as well as among all disciplines for outstanding research contribution (graduate student).

20. Best Student Paper Award (APEMC - 2010)

A. Narayanan received the Best Student Paper Award for the paper, "Fast EMI Analysis of Massively Coupled Interconnects with Long Delay", in the IEEE Asia Pacific International Symposium on Electromagnetic Compatibility, Beijing, China, April 2010 (graduate student).

21. University Medal (2009)

N. Nakhla, was the recipient of the Senate medal given by the Carleton University for her Doctoral work on “Waveform Relaxation and Transverse Partitioning Algorithms for Simulation of Massively coupled Interconnects”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

22. Best IEEE Transactions Paper Award (T-AdvP - 2007)

P. Triverio, S. Grivet-Talocia, M. Nakhla, F. Canavero and R. Achar, “Stability, causality, and passivity in electrical interconnect models,” IEEE Transactions on Advanced Packaging (T-AdvP), pp. 795-808, Nov. 2007. This work was done in collaboration with Polytechnico di Torino and was selected as the best contributions paper for the year 2007 by IEEE T-AdvP (co-author).

23. University Medal (2005)

N. Nakhla, was the recipient of the University medal given by the Carleton University for her Masters work on “Passive Macromodeling of Multiconductor Transmission Line Interconnects”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

24. IBM Best Student Paper Award (EPEP - 2006)

D. Paul, M. Nakhla, R. Achar and A. Weisshaar, "A Passive Algorithm for Modeling Frequency-Dependent Parameters of Coupled Interconnects", IEEE 15th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 185-188, Oct. 2006, Phoenix, AZ (graduate student).

25. Senate Medal (2006)

D. Saraswat was the recipient of the Senate medal given by the Carleton University for his doctoral work, titled, “Global Compact Passive Macromodeling Algorithms for High-Speed Circuits”. This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

26. University Medal (2005)

27. Young Researcher of the Year - OCRI Futures Award (2005)

D. Saraswat was the recipient of the Young Researcher of the Year - OCRI (Ottawa-Carleton Research Institute) Futures Award. This medal is awarded to the most promising student researcher of the National Capital Region, evaluated based on the research accomplishments and its impact (graduate student).

28. Research Achievement Award (2004)

Recipient of the Research Achievement Award (RAA) by the Carleton University. Each year Carleton university recognizes few professors for their excellence in research. Award consists of a certificate and a research grant of $15,000.

29. IBM Best Student Paper Award (EPEP - 2004)

N. Nakhla, A. Ruehli, M. Nakhla, and R. Achar, "Simulation of Coupled Interconnects using Waveform Relaxation and Transverse Partitioning", IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 25-28, Oct. 2004, Portland, Oregon, USA (graduate student).

30. INTEL Best Student Paper Award (EPEP - 2003)

A. Dounavis, N. Nakhla, R. Achar and M. Nakhla, "Delay Extraction and Passive Macromodeling of Lossy Coupled Transmission Lines", IEEE 12th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 295-298, New Jersey, Oct. 2003 (co-author).

31. IMS Best Student Paper Award (3rd) - (IMS - 2003)

D. Saraswat, R. Achar and M. Nakhla, "Passive Macromodels of Microwave Subnetworks Characterized by Measured/Simulated Data", IEEE International Microwave Symposium, (IMS), pp. 999-1002, Philadelphia, USA, June 2003 (graduate student).

32. Senate Medal (2003)

D. Saraswat was the recipient of the Senate medal given by the Carleton University for his Masters work, titled, "Passive Macromodeling of Subnetworks Characterized by Tabulated Data". This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research achievement at the doctoral/masters level (graduate student).

33. IBM Best Student Paper Award (EPEP - 2002)

D. Saraswat, R. Achar and M. Nakhla, "A Fast Algorithm and Practical Considerations For Passive Macromodeling of Measured/Simulated Data", IEEE 11^thTopical Meeting on EPEP, Monterrey, CA, pp. 297-300, October 2002 (graduate student).

34. IBM Best Student Paper Award (EPEP - 2001)

P. Gunupudi, R. Khazaka, A. Dounavis, R. Achar and M. Nakhla, "Global multi-level reduction technique for nonlinear simulation of high-speed interconnects", Proc. IEEE Electrical Performance of Electronics Packaging, Boston, MA, Oct. 2001, pp. 259-262 (co-author).

35. NSERC Doctoral Medal (2000)

Recipient of the prestigious NSERC doctoral medal for the doctoral work on high-speed interconnect analysis. Only four such medals are given in a year throughout Canada, among all Canadian universities as well as among all disciplines for outstanding research contribution.

36. University Medal (1998)

Recipient of the prestigious University Medal given by the Carleton University for the Ph. D. work, titled, "Model-reduction techniques for high-speed interconnect analysis". This medal is given in each convocation ceremony, only when merited, to a graduate student for outstanding research and academic achievement.

37. Micronet Best Student Paper Award (1998)

R. Achar and M. Nakhla "A new algorithm for efficient simulation of on-chip integrated components", Micronet Annual Workshop on Circuits and Systems in Canada, Feb. 1998, Ottawa, Canada.

38. INTEL Best Student Paper Award (EPEP-1998)

P. Gunupudi, M. Nakhla and R. Achar, "Efficient simulation of high speed distributed interconnects using Krylov-subspace techniques", IEEE 7th Topical meeting on Electrical Performance of Electronic Packaging, NY, Oct. 1998, pp. 295-298 (co-author).

39. Strategic Microelectronics Consortium (SMC) Industrial Collaboration Award (1997)

R. Achar and M. Nakhla "A novel method for efficient simulation of high-speed VLSI designs", Symposium on R&D in Microelectronics in Canada, June 1997, Ottawa, Canada. This paper was judged as the best demonstrated research by the awards panel and was awarded the first ever Strategic Microelectronics Consortium (SMC) Industrial Collaboration Award.

40. Canadian Microelectronics Corporation (CMC) International Travel Award (1996)

R. Achar and M. Nakhla, "An efficient algorithm for addressing high-frequency effects in VLSI interconnects with full-wave models", Symposium on R&D in Microelectronics in Canada, June 1996, (Ottawa, Canada). This presentation was judged as the best CAD (Computer-Aided Design) paper focused on microelectronics or microsystems in the symposium and was awarded the 1996 CMC International Travel Award.

Professional Activities (Major Professional activities in the recent past are listed below)

· Member of Board of Governors (2023) – IEEE EMCS

Serving as the member of the BoG of the Electromagnetic Compatibility Society.

· Chair, “Distinguished Lecturer Program” (DLP) of IEEE EMC Society (Since 2017)

Serving as the chair of the “Distinguished Lecturer Program” (DLP) of the IEEE Electromagnetic Compatibility Society (EMCS). The responsibility in this task includes, soliciting DL speaker nominations, selecting DL speakers, DL talk/travel approvals, administering the DL budget and related interactions with the EMCS chapter chairs worldwide.

· Distinguished Lecturer of EDS Society (Since 2017)

Serving as the “Distinguished Lecturer”, under the DLP program by the IEEE Electronic Devices Society (EDS) since 2017.

· Distinguished Lecturer of EPS Society (Since 2020)

Serving as the “Distinguished Lecturer”, under the DLP program by the IEEE Electronic Packaging Society (EDS) since 2020.

· Founder and the General Chair for HPCPS ((2012, 2013, 2014, 2015, 2017)

Founder and the General Chair for HPCPS (IEEE International Workshop on High-Performance Chip, Package and Systems: www.hpcps.org) (2012, 2013, 2014, 2015, 2017) IEEE International Workshop on High Performance of Chip, Package and Systems (HPCPS)" (Ottawa, Canada).

· Publications Chair of EDAPS ((2016)

Publications Chair of EDAPS-2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Honolulu, HI, 2016.

· General Co-Chair of SIPI ((2015)

General Co-Chair of -2015 (IEEE International Conference on Signal Integrity and Power Integrity, Ottawa, Canada.

· General Co-Chair of NEMO-2015 ((2015)

General Co-Chair of NEMO-2015 (IEEE International conference on Electromagnetic and Multi-physics based modeling, simulation and optimization for RF, microwave and terahertz applications, Ottawa, Canada; www.nemo-ieee.org).

· Guest Editor IEEE Transactions on CPMT ((2013)

Guest Editor, Special issue of IEEE T-CPMT on "Macromodeling and Variability in Nanoscale Designs" (2013).

Guest Editor, Special issue of IEEE T-CPMT on "3D-ICs and Interconnects" (2013).

· Distinguished Lecturer of CASS Society (2011, 2012)

Selected as the “Distinguished Lecturer”, under the DLP program by the Circuits and Systems Society (CASS) for years 2011 & 2012.

· General Co-Chair of EPEPS (2010, 2011)

General Co-Chair for the "IEEE International Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)" for years 2010 (Austin, Texas) & 2011 (San Jose, California). EPEPS is the world’s premier conference focused on signal integrity, power integrity, advanced packaging methodologies and high-speed interconnects.

· Chair, ISE Committee of EPEPS (2014)

o Chair, Industry Advisory, Sponsorship, and Exhibits (ISE) Committee of EPEPS (2014)

o Chair, Technical Program Committee of EPEPS (2011)

o Chair, Embedded Tutorials Committee (2007-2009)

· TPC Co-Chair (HSI-2012)

Technical Program Committee Co-Chair for the "IEEE International High Speed Interconnects Symposium – From Silicon to Systems", April 2012, Dallas, TX, USA.

· Founding Faculty Member of Canada-India Center (Since 2011)

Founding Faculty Member of Canada-India Center for Excellence and instrumental in several collaborative initiatives with premier institutions in India through this center.

· Chair – Signal and Power Integrity Subcommittee of ASP-DAC TPC (2012, 2013)

o IEEE International Asia-Pacific Design Automation Conference

· Chair - Interconnect Modeling/Simulation, Signal Integrity Subcommittee of ICCAD TPC (2006, 2007)

o IEEE International Conference on Computer-Aided Design

· Track Co-Chair, VLSI Design (2022)

o Co-Chair of the TPC Track on Packaging and Interconnects of IEEE International Conference on VLSI Design 2022, India

· Chair - Joint Chapters of CASS/SSCS/EDS of Ottawa IEEE Section (since 2005)

Chair of Joint Chapters of Circuits & Systems Society, Solid-State-Circuits Society and Electronic-Devices Society of Ottawa IEEE Section (Vice Chair: 2003-2005).

Under the leadership of Prof. Achar, the joint chapter has arranged over 100 talks and 2 international workshops, with speakers coming from around the globe. The chapter was recognized with several awards during this period for its activities (prominent ones listed below):

o 2016 IEEE Circuits and Systems Society Chapter Subsidy Grant

o 2015 Best Chapter of the Year by the IEEE Ottawa Section

o 2015 IEEE Circuits and Systems Society Chapter Subsidy Grant

o 2015 IEEE Solid State Circuits Society Chapter Subsidy Grant of

o 2014 IEEE Circuits and Systems Society Chapter Subsidy Grant

o 2013 IEEE Circuits and Systems Society Region 1-7 Chapter of the Year Award

o 2013 Best Chapter of the Year by the IEEE Ottawa Section

o 2013 IEEE Circuits and Systems Society Outreach Grant for Innovative Projects

o 2012 IEEE Circuits and Systems Society Surplus Grant for Innovative Projects

o 2009 IEEE Circuits and Systems Society Region 1-7 Chapter of the Year Award

o 2008 Best Chapter of the Year by the IEEE Ottawa Section

· Steering/Executive Committee Member of:

o SIPI ((2015): IEEE International Conference on Signal Integrity and Power Integrity, Ottawa, Canada.

o NEMO ((2015): NEMO-2015 (IEEE International conference on Electromagnetic and Multi-physics based modeling, simulation and optimization for RF, microwave and terahertz applications, Ottawa, Canada; www.nemo-ieee.org).

o EPEPS (2010-2013): IEEE International Conference on Electrical Performance of Electronic Packaging and Systems

o HPCPS (2012-2017): IEEE International Workshop on High Performance of Chip, Package and Systems

o EDAPS (2010-2013): IEEE International Conference on Electrical Advanced Packaging and Systems

· Member of the Committees of:

o TC-12 EDMS (2007 - Present): Technical Committee on Electrical Design, Modeling and Simulation : TC-12 EDMS sets the technological and professional roadmap for the area of electrical design, modeling and simulation roadmap under the umbrella of IEEE Electronic Packaging Society

o TC-2 DAC (2012-2017): Technical Committee on Design Automation: TC-2-DAC sets the technological and professional roadmap for the area of computer-aided design under the umbrella of IEEE Microwave Theory and Techniques (MTT) Society

o TC-10 SIPI (2014-2016): Technical Committee on Signal and Power Integrity : TC-10 SIPI sets the technological and professional roadmap for the area of signal and power integrity roadmap under the umbrella of IEEE Electromagnetic compatibility Society

o IEEE vTools Strategic Committee (2014) : vTools is an enabling platform for thousands of IEEE volunteers in their mission of “connect, create, communicate and complete” for their IEEE activities.

o EC-ICOBC (2010-2012): Election Committee, Indo Canada Ottawa Business Chamber, Board of Directors Election

· Technical Program Committee Member of (selected/recent):

o APEMC/INCEMIC (2023): Joint Conference of 14th edition of Asia Pacific Electro Magnetic Compatibility symposium & the 16th edition of International Conference on Electromagnetic Interference & Compatibility

o EPEPS (2007-Present): IEEE International Conference on Electrical Performance of Electronic Packaging and Systems

o EDAPS (2007-Present): IEEE International Conference on Electrical Advanced Packaging and Systems

o SPI (2008-Present): IEEE International Conference on Signal Propagation on Interconnects

o HPCPS (2012-2017): IEEE International Workshop on High-Performance Chip, Package and Systems

o ICNFA (2012-Present): International Conference on Nanotechnology: Fundamentals and Applications

o ASP-DAC (2010-2013): IEEE International Asia-Pacific Design Automation Conference

o IASTED (2013): International Conference on Modelling and Simulation, Banff, Canada

o LASCAS (2012, 2013): IEEE Latin American Symposium on Circuits and Systems

o MNRC (2009): IEEE International Microsystems and Nanoelectronics Research Conference

o IWMS (2008): IEEE MTT-S International Microwave Workshop Series

o ICCAD (2003-2007): IEEE International Conference on Computer-Aided Design

o NEWCAS (2007 - CAD Track Chair): IEEE International North Eastern Circuits and Systems Conference

o IDV (2006): IEEE International Workshop on Interconnect Design and Variability

o ISSSE (2007): International Symposium on Signals, Systems, and Electronics - 2007

· International Advisory Committee Member of:

o APCCAS (2010): IEEE International Asia-Pacific Conference on Circuits and Systems

· Practicing Professional Engineer (P. Eng.) of Ontario (Since 2001)

· Senior Member of the IEEE (Since 2005; Member since 2000)

· Member of (selected/recent):

o CASS: IEEE Circuits and Systems Society

o SSCS: IEEE Solid-State Circuits Society

o MTTS: IEEE Microwaves Society

o EDS: IEEE Electronic Devices Society

o EMCS: IEEE Electromagnetic Compatibility Society

o EPS: IEEE Electronic Packaging Society

o ICOBC: Indo Canada Ottawa Business Chamber

o AP-ISA: India Semiconductor Association Awards Panel (2007)

o SCC: Standards Council of Canada (2007-Present)

· Frequent Reviewer for Several Leading International IEEE Transactions (selected/recent)

o T-CAS: IEEE Transactions on Circuits and Systems

o T-CAD: IEEE Transactions on Computer-Aided Design

o T-AdvP: IEEE Transactions on Advanced packaging

o T-CPMT: IEEE Transactions on Components, Process and Manufacturing Technology

o T-MTT: IEEE Transactions on Microwave Theory and Techniques

o T-SIPI: IEEE Transactions on Signal and Power Integrity

o T-EMC: IEEE Transactions on Electromagnetic Compatibility IEEE Journal on Multiscale and Multiphysics Computational Techniques

o J-MMCT: IEEE Journal on Multiscale and Multiphysics Computational Techniques

o MWL: IEEE Microwave Letters

o Proc-IEEE: Proceedings of IEEE

o Proc-IEE: Proceedings of IEE

o J-VLSID: Journal of VLSI Design, Hindawi Publications

o J-RFMCAD: Wiely International Journal of RF and Microwave Computer-Aided Engineering

· Frequent Reviewer for Several Books & Publishers (selected/recent)

o John Wiely & Sons, IEEE Press .....

· Frequent Reviewer for Several for Leading Grant Agencies (selected/recent):

o NSERC Discovery Grant Applications (2003 - 2009)

o NSERC Idea to Innovation (I2I) Program - 2008

o MITACS Accelerate Program (2003 - 2009)

o CITO Grant Applications - 2004, 2005, 2006 ....

o European Grants

· Served as Judge in Several Best Student Paper Competitions

o More than 10 such activities

· Session Chair, Organizer of Special Sessions, Workshops

o More than 30 such activities

· Moderator for Panel Discussion, Panelist (selected/recent)

o VAIBHAV Summit-2020, EPEPS-2009, 2011, 2012, IDV-2006

Academic Activities (selected/recent)

· Seminar Co-Ordinator, Seminar Co-ordinator for the Department of Electronics (since 2003)

· Member of the Department Hiring Committee (2021, 2022).

· Member of the University Promotions Appeals Committee (2020, 2011).

· Chair, Carleton University Scholarship's Committee (2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018)

· Member of Carleton University Scholarship's Committee (2008-2018)

· Member of University Promotions Committee (2015, 2016, 2017, 2018).

· Member, Faculty of Engineering & Design Research Advisory Committee (since 2010,2011,2012,2013, 2014)

· Member, Carleton University Senate (2006, 2007, 2008, 2009)

· Member, Carleton University Senate Executive Committee (2007)

· Departmental Web Editor (2003, 2004, 2009, 2010)

· Member, FED Search Committee for Associate Dean of Research (2009)

Member, Undergraduate Recruitment Committee (since 2007)

Representing the department in various undergraduate recruitment events, such as Ontario University Fair (OUF), Toronto Parents Evening, Carleton University Day, etc., since 2007)

· Member of the Computing Network Committee (2002-2003)

· Served as Examiner (both External/Internal) for Several Thesis Exams

o 50+ Ph. D. Related Exams (Defense, Proposal (Oral), and Comprehensive Exams)

o 30+ M. A. Sc. Thesis Exams

Education:

Ph. D. (Electrical Engineering) 1993-1998	Carleton University, Ottawa, Canada
M.E. (Microelectronics Eng) 1991-92	Birla Institute of Technology and Science, Pilani, India
B.E. (Electronics Engineering) 1985-90	R.V. College of Engineering, Bangalore University, Bangalore, India

Experience:

Professor 07/2010 to present Associate Professor 07/2005 to 06/2010 Assistant Professor 07/2000 - 06/2005 Dept. of Electronics Engineering, Carleton University, Ottawa, Canada	Assignments include research, teaching, graduate/undergraduate student supervision and academic responsibilities. Current/past research collaborations in the area of simulation/modeling of high-speed circuits and systems include several leading global companies, such as: · IBM T. J. Watson Research Center, Yorktown Heights · Analog Devices, Boston · Computer Simulation Technology (CST), Germany, · Mentor Graphics · Celestica Inc., Ottawa, Canada · Gennum Corporation, Ottawa, Canada · Optem Engineering, Calgary, Canada · Javelin Design Automation, Ottawa, Canada · Nortel Networks, Ottawa, Canada, etc.
Research Engineer 09/93 - 08/95 10/95- 08/98 Dept. of Electronics Engineering, Carleton University, Ottawa, Canada	Involved in contributing and setting the directions for the research done under the NSERC-NORTEL Chair (CAE group) at Carleton University. Collaborated with several industries to provide solutions for high-speed design applications. The companies include, Cadence Design Systems: Ottawa/Chelmsford, Nortel Networks: Ottawa, Gennum Corporation: Toronto, IBM: Austin/Poughskpee/ Yorktown-Heights, Intel: Sacramento, etc.
Exchange Trainee 05/95 to 09/95 Electrical simulation Group, T. J. Watson Research Centre IBM, New York	Involved in the development and implementation of interconnect simulation algorithm for the next generation simulation tool of IBM, ACES (Adoptively controlled Explicit Simulator).
R&D Engineer 01/93 to 09/93 ASIC Design Centre, Larsen and Toubro Engineers Limited, Mysore, India	Involved in the development of an ASIC for the “call processor card” of Centre for Development of Telematics (C-DoT), India. The CP card (mediator between the line and terminal cards), which is responsible for handling on/off-hook, metering signals etc., had 108 LSI chips. Responsible for design, schematic and timing verification.
R & D Projects 04/89 to 12/92	During this period, worked on several R&D projects in various capacities, (R&D Engineer, Trainee, Assistant Lecturer) in premier research labs and institutions in India, including: (a) Central Electronics Engineering Research Institute (CEERI), Pilani (b) Indian Institute of Science (IISc), Bangalore (c) Bharat Heavy Electrical Limited (BHEL), Bangalore (d) Birla Institute of Technology and Science (BITS), Pilani (e) R.V. College of Engineering (RVCE), Bangalore University

Hobby: Yoga

Multimedia Book Series on Signal Integrity:

Publishers: OMNIZ Global Knowledge Corporation
in Partnership with IEEE (Education Partners) and Amazon.com

Authors: M. Nakhla and R. Achar, First Edition: May 01, 2002

1. Introduction to High-Speed Circuit and Interconnect Analysis
     ((ISBN 0-9731047-0-8)
2. Principles of Circuit and Interconnect Simulation
     ((ISBN 0-9731047-1-6)
3. Fundamentals of Multiconductor Transmission Line Analysis
     ((ISBN 0-9731047-2-4)
4. Model-Reduction Algorithms: Principles, AWE, CFH and Macromodeling
     ((ISBN 0-9731047-3-2)
5. Theory of Eigenvalue Analysis and Orthogonal Systems
     ((ISBN 0-9731047-4-0)
6. Krylov Subspace Techniques for Circuit and Interconnect Analysis
     ((ISBN 0-9731047-5-9)

Refereed Journal Papers

1. A. Javaid, R. Achar and J. Tripathi, "Development of Knowledge Based Artificial Neural Networks for Analysis of PSIJ in CMOS inverter Circuits", IEEE Transactions on Microwave Theory and Techniques, Accepted for publication, pp. 1-10, Oct. 2022.

2. J. Tripathi, M. Illikal, H. Shrimali and R. Achar, "Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters, IEEE Access, pp. 100172-100177, Sept. 2022.

3. W. K. Lee and R. Achar, “Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation”, IEEE Access, Accepted for publication, pp. 1-11, July 2022.

4. I. Erdin and R. Achar, "A Domain Decomposition Approach for Assessment of Decoupling Capacitors in Practical PDNs", IEEE Transactions on Signal Integrity and Power Integrity, Accepted for publication, pp. 1-11, July 2022.

5. W. K. Lee, H. Seo, S. O. Hwang, R. Achar, A. Karmakar and J. Mera “DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs”, IEEE Transactions on Circuits and Systems - I, Accepted for publication, pp. 1-14, May 2022.

6. I. Erdin and R. Achar, "An Effective Global Approach for Assessment of Decoupling Capacitors on Mixed Planar and Transmission Line PDNs", IEEE Journal on Multiscale and Multiphysics Computational Techniques, pp. 176-185, July 2022.

7. I. Erdin and R. Achar, "MCB-DPO: Multiport Constrained Barrier Method-Based Decoupling Capacitor Placement Optimization on Irregularly Shaped Planes, IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 665-675, Apr. 2022.

8. R. Kumar, S. Likithnarayan, S. Kumar, S. Roy, B. Kaushik, R. Achar and R. Sharma, "Knowledge-Based Neural Networks for Fast Design Space Exploration of Hybrid Copper-Graphene On-Chip Interconnect Networks", IEEE Transactions on Electromagnetic Compatibility, pp. 182-195, Feb. 2022.

9. W. K. Lee and R. Achar, “GPU Accelerated Adaptive PCBSO Mode based Hybrid RLA for Sparse LU Factorization”, IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 2320 - 2330, Nov. 2021.

10. I. Erdin and R. Achar, "Pin Impedance Based Figure of Merit with Mutual Coupling (PMC-FOM) for Assessment of A Decoupling Capacitor on Polygonal Parallel Plates, IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1343 - 1354, Sept. 2021.

11. S. Ganeshan, N. Kumar and R. Achar and W. K. Lee, "GVF: GPU based Vector Fitting for Modelling of Multiport Tabulated Data Networks", IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1375-1387, Aug. 2020.

12. R. Kumar, A. Kumar, S. Guglani, S. Kumar, S. Roy, B. Kaushik, R. Sharma and R. Achar, "A Temperature and Dielectric Roughness-Aware Matrix Rational Approximation (MRA) Model for the Reliability Assessment of Copper-Graphene Hybrid On-Chip Interconnects", IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1454 - 1465, Jun. 2020.

13. J. N. Tripathi, P. Arora, H. Shrimali and R. Achar, "Efficient Jitter Analysis for a Chain of CMOS Inverters", IEEE Transactions on Electromagnetic Compatibility, pp. 1-11, pp. 229-239, Feb. 2020.

14. I. Erdin and R. Achar, "Authors Reply: Decoupling Capacitor Placement on Resonant Parallel-Plates Via Driving Point Impedance, IEEE Transactions on Microwave Theory and Techniques, pp. 836, Feb. 2020.

15. I. Erdin and R. Achar, "Multi-Objective Optimization of Decoupling Capacitors for Placement and Component Value, IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1976-1983, Oct. 2019.

16. J. N. Tripathi, M. S. Illikal, H. Shrimali and R. Achar, "A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers, IEEE Access, pp. 125240 -125252, Sept. 2019.

17. J. N. Tripathi, A. Javaid and R. Achar, "Modeling the Combined Effects of Transmission Media and Ground Bounce on Power Supply Induced Jitter, IEEE Transactions on Electromagnetic Compatibility, pp. 11183-1190, Aug. 2019.

18. I. Erdin and R. Achar, "Decoupling Capacitor Placement on Resonant Parallel-Plates Via Driving Point Impedance, IEEE Transactions on Microwave Theory and Techniques, pp. 2162-2171, June 2019.

19. W. Lee, R. Achar and M. S. Nakhla, "Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 2518-2529, Nov. 2018.

20. I. Erdin and R. Achar, "Multipin Optimization Method for Placement of Decoupling Capacitors Using a Genetic Algorithm", IEEE Transactions on Electromagnetic Compatibility, pp. 1662-1669, Mar. 2018.

21. I. Erdin and R. Achar, "Efficient Decoupling Capacitor Placement Based on Driving Point Impedance", IEEE Transactions on Microwave Theory and Techniques, pp. 669-677, Feb. 2018.

22. I. Erdin and R. Achar, "Modeling of Asymmetric Differential Striplines Including Crossing Junction Discontinuities”, IEEE Transactions on Electromagnetic Compatibility, pp. 50-58, Feb. 2018.

23. J. Tripathi, R. Achar, and R. Malik, "Fast Analysis of Time Interval Error in Current-Mode Drivers", IEEE Transactions on VLSI, pp. 367-377, Feb. 2018. (Research Collaboration with ST Microelectonics, Noida, India).

24. I. Erdin, R. Achar and K. Erdin, "Power Integrity Aware Approach to Dynamic Analysis of Buck Converters, IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 32-40, Jan. 2018.

25. J. Tripathi, R. Achar and R. Malik, "Efficient Modeling of Power Supply Induced Jitter in Voltage Mode Drivers (EMPSIJ)”, IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1691-1701, Oct. 2017 (Research Collaboration with ST Microelectonics, Noida, India).

26. Y. Tao, B. Nouri, M. Nakhla, and R. Achar, "Variability Analysis Via Parametrized Model Order Reduction and Numerical Inversion of Laplace Transform”, IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 678-686, May 2017.

27. B. Nouri, M. Nakhla, and R. Achar, "Efficient Simulation of Nonlinear Transmission Lines via Model Order Reduction," IEEE Transactions on Microwave Theory and Techniques, pp. 673-683, Mar. 2017.

28. M. Farhan, M. Nakhla, E. Gad and R. Achar, "Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits", IEEE Transactions on Very Large Scale Integration, pp. 261-270, Jan. 2017.

29. M. Rufuie, E. Gad, M. Nakhla and R. Achar, "Fast Variability Analysis of General Nonlinear Circuits Using Decoupled Polynomial Chaos," IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1860-1871, Dec. 2015.

30. D. Paul, R. Achar, M. Nakhla and N. Nakhla, "Addressing Partitioning Issues in Parallel Circuit Simulators", IEEE Transactions on Very Large Scale Integration, pp. 2713-2723, Dec. 2014.

31. M. Farhan, E. Gad, M. Nakhla and R. Achar, "High-Order and A-Stable Envelope Following Method for Transient Simulations of Oscillatory Circuits", IEEE Transactions on Microwave Theory and Techniques, pp. 3309-3314, Dec. 2014.

32. T-A Pham, E. Gad, M. Nakhla and R. Achar, "Decoupled Polynomial Chaos and its Applications to Statistical Analysis of High-Speed Interconnects", IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1634-1647, Oct. 2014.

33. M. Farhan, N. Nakhla, M. Nakhla and R. Achar, "Fast Transient Analysis of Tightly Coupled Interconnects Via Overlapping Partitioning and Model Order Reduction", IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1648-1656, Oct. 2014.

34. M. Farhan, E. Gad, M. Nakhla and R. Achar, "Parallel Simulation of Large Linear Circuits with Nonlinear Terminations Using High-Order Stable Methods," IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1201-1211, July 2014.

35. M. Rufuie, E. Gad, M. Nakhla and R. Achar, "Generalized Hermite Polynomial Chaos for Variability Analysis of Macromodels Embedded in Nonlinear Circuits," IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 673-684, April 2014.

36. D. Paul, M. Nakhla, R. Achar and N. Nakhla, "Parallel Circuit Simulation via Binary Link Formulations (PvB)", IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 768- 782, May 2013.

37. B. Nouri, M. Nakhla, and R. Achar, "Optimum Order Estimation for Reduced Macromodels based on a Geometrical Approach to Model Order Reduction," IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1218-1227, July 2013 (Best IEEE CPMT Transaction Paper Award - 2013).

38. B. Nouri, M. Nakhla, and R. Achar, "Efficient Reduced-Order Macromodels of Massively Coupled Interconnect Structures via Clustering," IEEE Transactions on Transactions on Components, Packaging and Manufacturing Technology, pp. 826-840, May 2013.

39. M. Farhan, E. Gad, M. Nakhla and R. Achar, "New Method for Fast Transient Simulation of Large Linear Circuits using High-Order Stable Methods, IEEE Transactions Components, Packaging and Manufacturing Technology, pp. 661-669, Apr. 2013.

40. M. Farhan, N. Nakhla, M. Nakhla and R. Achar, "Fast Simulation of Microwave Circuits with Nonlinear Terminations using High-Order Stable Methods," IEEE Transactions on Microwave Theory and Techniques, pp. 360-371, Jan. 2013.

41. A. Saini, M. Nakhla, and R. Achar, "Generalized Time-Domain Adjoint Sensitivity Analysis of Distributed MTL Networks," IEEE Transactions on Microwave Theory and Techniques, pp. 3359-3368, Nov. 2012.

42. M. Farhan, N. Nakhla, M. Nakhla, R. Achar and A. Ruehli, "Overlapping Partitioning Techniques for Simulation of Strongly Coupled Distributed Interconnects," IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1193-1201, July 2012.

43. E. Gad, M. Nakhla, R. Achar and Y. Zhou, "Structural Characterization and Efficient Implementation Techniques for A-stable High-Order Integration Methods", IEEE Trans. on Computer Aided Design, pp.101-108, Jan. 2012.

44. R. Achar "High-Speed Interconnect Modeling", IEEE Microwave Magazine, pp. 61-74, Aug. 2011.

45. A. Charest, M. Nakhla, R. Achar and D. Saraswat, "Passivity Verification of Delayed Rational Function based Macromodels of Tabulated Networks Characterized by Scattering Parameters", IEEE Transactions on CPMT, pp. 386 - 398, Mar. 2011.

46. R. Achar, M. Nakhla, H. Dhindsa, A. Sridhar, D. Paul and N. Nakhla, "Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation Techniques", IEEE Transactions on Very Large Scale Integration, pp. 319-332, Feb. 2011.

47. N. Nakhla, M. Nakhla, and R. Achar, "A General Approach for Time-Domain Sensitivity Analysis of High-Speed Interconnects," IEEE Transactions on Microwave Theory and Techniques, pp. 46-55, Jan. 2011.

48. N. Nakhla, M. Nakhla, and R. Achar, "Simplified Delay-Extraction Based Passive Transmission Line Macromodeling Algorithm," IEEE Transactions on Advanced Packaging, pp. 498-509, May 2010.

49. B. Nouri, R. Achar and M. Nakhla, "z-Domain Orthonormal Basis Functions for Physical System Identifications", IEEE Transactions on Advanced Packaging, pp. 293-307, Feb. 2010.

50. A. Charest, M. Nakhla, R. Achar, D. Saraswat, N. Soveiko and I. Erdin, "Time-Domain Delay Extraction based Macromodeling Algorithm for Long Delay Networks", IEEE Transactions on Advanced Packaging, pp. 219-235, Feb. 2010.

51. D. Paul, N. Nakhla, R. Achar and M. Nakhla "Parallel Simulation of Massively Coupled Interconnect Networks", IEEE Transactions on Advanced Packaging, pp. 115-127, Feb. 2010.

52. N. Soveiko, M. Nakhla and R. Achar, "Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures", IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 605-607, Jan 2010.

53. A. Charest, M. Nakhla and R. Achar, "Delay Extracted Stable Rational Approximations for Tabulated Networks with Periodic Reflections", IEEE Microwave Letters, pp. 768-770, Dec. 2009.

54. A. Charest, M. Nakhla and R. Achar, "Scattering Domain Passivity Verification and Enforcement of Delayed Rational Function Based Macromodels", IEEE Microwave Letters, pp. 605-607, Oct. 2009.

55. E. Gad, M. Nakhla, R. Achar and Y. Zhou, "A-Stable and L-Stable High-Order Integration Methods for Stiff Differential Equations", IEEE Trans. on Computer Aided Design, pp. 1359-1372, Sept. 2009.

56. C. Chen, D. Saraswat, R. Achar, E. Gad, M. Nakhla and M. C. E. Yagoub, "Passivity Compensation Algorithm for Method of Characteristics Based Multiconductor Transmission Line Interconnect Macromodels", IEEE Trans. on VLSI, pp. 1061-1072, Aug. 2009.

57. A. Sridhar, N. Nakhla, R. Achar, M. Nakhla and A. Ruehli, "Fast EMI Analysis of High-Speed Interconnects via Waveform Relaxation and Transverse Partitioning", IEEE Transactions on Electromagnetic Compatibility, pp. 358 - 371, May 2009.

58. D. Paul, M. Nakhla, R. Achar and A. Weisshaar, "Broadband Modeling of High-Frequency Microwave Devices", IEEE Transactions on Microwave Theory and Techniques, pp. 361-373, Feb. 2009.

59. A. Charest, R. Achar, M. Nakhla and I. Erdin, "Delay extraction-based passive macromodeling techniques for transmission line type interconnects characterized by tabulated multiport data", Journal of Analog Signal Processing, Springer, pp. 13-25, Aug. 2008.

60. G. Shinh, R. Achar, N. Nakhla, M. Nakhla, and I. Erdin, "A Simplified Time-Domain Macromodel for Analysis of MTLs in the Presence of Incident Fields (SiMMIF)", IEEE Transactions on Electromagnetic Compatibility, pp. 375-389, May 2008.

61. C. Chen, D. Saraswat, R. Achar, E. Gad, M. Nakhla and M. C. E. Yagoub, "A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs with FD-PUL Parameters Using Integrated Congruence Transform, IEEE Trans. on Computer Aided Design, pp. 574-578, Mar. 2008.

62. A. Charest, D. Saraswat, M. Nakhla, R. Achar and N. Soveiko, "Compact Macromodeling of High-Speed Circuits via Delayed Rational Functions", IEEE Microwave Letters, pp. 828-830, Dec. 2007.

63. W. Tseng, C. Chen, M. Nakhla and R. Achar, "Passive Order Reduction for RLC Circuits with Delay Elements", IEEE Transactions Advanced Packaging, pp. 830-840, Nov. 2007.

64. P. Triverio, S. Grivet-Talocia, M. Nakhla, F. Canavero and R. Achar, “Stability, causality, and passivity in electrical interconnect models,” IEEE Transactions on Advanced Packaging, pp. 795-808, Nov. 2007 (Best IEEE AdvP Transaction Paper Award - 2007).

65. E. Gad, C. Chen, M. Nakhla and R. Achar, "Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform", IEEE Trans. on Computer Aided Design, pp. 1139-1149, June 2007.

66. N. Nakhla, A. Ruehli, M. Nakhla, R. Achar and C. Chen, "Waveform Relaxation Techniques for Simulation of Coupled Interconnects with Frequency-Dependent Parameters", IEEE Transactions on Advanced Packaging, pp. 257-269, May 2007.

67. E. Gad, C. Chen, M. Nakhla and R. Achar, "Passivity Verification in Delay-Based Macromodels of Multiconductor Electrical Interconnects", IEEE Trans. on Advanced Packaging, pp. 246-256, May 2007.

68. R. Achar, "High-Speed Effects and Signal Integrity", The ICFAI Journal of Science and Technology, pp. 7-18, vol. 3, No. 1, Mar. 2007 (Invited Article).

69. D. Saraswat, R. Achar and M. Nakhla, "Passivity Enforcement via Reciprocal Systems for Interconnects with Large Order Macromodels", IEEE Transactions on Very Large Scale Integration, pp. 48-57, Jan. 2007.

70. G. Shinh, N. Nakhla, R. Achar, M. Nakhla, A. Dounavis and I. Erdin, "Fast Transient Analysis of Incident Field Coupling to Multiconductor Transmission Lines", IEEE Transactions on Electromagnetic Compatibility, pp. 57 - 73, Feb. 2006.

71. P. Pai, E. Gad, R. Achar, R. Khazaka and M. Nakhla, "A Projection-Based Reduction Approach to Computing Sensitivity of Steady-State Response of Nonlinear Circuits", INFORMS Journal of Computing, vol. 18, no. 2, pp. 173-185, Spring 2006.

72. N. Nakhla, A. Ruehli, M. Nakhla, and R. Achar, "Simulation of coupled interconnects using waveform relaxation and transverse partitioning", IEEE Transactions on Advanced Packaging, pp. 78-87, Feb. 2006.

73. N. Nakhla, A. Dounavis, M. Nakhla, and R. Achar, "Delay-Extraction Based Sensitivity Analysis of Multiconductor Transmission Lines with Nonlinear Terminations," IEEE Transactions on Microwave Theory and Techniques, pp. 3520 - 3530, Nov. 2005.

74. E. Gad, C. Chen, M. Nakhla and R. Achar, "Passivity Verification in Delay-Based Macromodels of Electrical Interconnects", IEEE Trans. on Circuits and Systems, pp. 2173 - 2187, Oct. 2005.

75. D. Saraswat, R. Achar and M. Nakhla, "Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data, IEEE Transactions on Very Large Scale Integration, pp. 819-832, July 2005.

76. N. Nakhla, A. Dounavis, R. Achar and M. Nakhla, "DEPACT: Delay Extraction and Passive Macromodeling of Lossy Coupled Transmission Lines", IEEE Transactions on Advanced Packaging, pp. 13-23, Feb. 2005.

77. D. Saraswat, R. Achar and M. Nakhla, "Passive Reduction Algorithm for RLC Interconnect Circuits with Embedded State-Space Systems (PRESS)", IEEE Transactions on Microwave Theory and Techniques, pp. 2215 - 2226, October 2004.

78. D. Saraswat, R. Achar and M. Nakhla, "A Fast Algorithm and Practical Considerations For Passive Macromodeling Of Measured/Simulated Data", IEEE Transactions on Advanced Packaging, pp. 57-70, Feb. 2004.

79. A. Dounavis, R. Achar and M. Nakhla, "Addressing Transient Errors in Passive Macromodels of Distributed Transmission Line Networks", IEEE Transactions on Microwave Theory and Techniques, Vol. 50, pp. 2759 -2768, Dec 2002.

80. A. Dounavis, R. Achar and M. Nakhla "Efficient Sensitivity Analysis of Lossy Multiconductor Transmission Lines with Nonlinear Terminations", IEEE Transactions on Microwave Theory and Techniques, Vol. 49, pp. 2292 -2299, Dec. 2001.

81. I. Erdin, A. Dounavis, R. Achar and M. Nakhla, "A SPICE Model for Incident Field Coupling to Lossy Multiconductor Transmission Lines", IEEE Transactions on Electromagnetic Compatibility, Vol. 43, pp 485 -494, November 2001.

82. A. Dounavis, R. Achar and M. Nakhla, "A General Class of Passive Macromodels for Lossy Multiconductor Transmission Lines", IEEE Transactions on Microwave Theory and Techniques, Vol. 49, pp. 1686 -1696, October. 2001.

83. R. Achar and M. Nakhla, "Simulation of High-Speed Interconnects", Proceedings of The IEEE, Vol. 89, pp. 693-728, May 2001 (** INVITED PAPER **).

84. A. Dounavis, E. Gad, R. Achar and M. Nakhla, "Passive model-reduction of multiport distributed networks including frequency-dependent parameters", IEEE Trans. on Microwave Theory and Techniques, pp. 2325-2334, Dec. 2000.

85. I. Erdin, M. Nakhla and R. Achar, "Circuit analysis of electromagnetic radiations and field coupling effects for networks with embedded full-wave modules", IEEE Transactions on Electromagnetic compatibility (EMC), pp. 449-460, Nov. 2000.

86. A. Dounavis, R. Achar and M. Nakhla, "Efficient passive circuit models for distributed networks with frequency-dependent parameters", IEEE Transactions on Advanced Packaging, pp. 382-392, Aug. 2000.

87. P. Gunupudi, M. Nakhla and R. Achar, "Simulation of high-speed distributed interconnects using Krylov-subspace techniques", IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 799-808, July 2000.

88. R. Achar, M. Nakhla, P. Gunupudi and E. Chiprout, "Passive interconnect reduction algorithm for distributed/measured networks", IEEE Trans. on Circuits and Syst, pp. 287 -301, Apr. 2000.

89. A. Dounavis, X. Li, M. Nakhla and R. Achar, "Passive closed-loop transmission line model for general purpose circuit simulators", IEEE Transactions on Microwave Theory and Techniques, pp. 2450-2459, Dec. 1999.

90. R. Achar and M. Nakhla, "Efficient transient simulation of embedded subnetworks characterized by S-parameters in the presence of nonlinear elements", IEEE Transactions on Microwave Theory and Techniques, vol. 46, pp. 2356-2363, Dec. 1998.

91. R. Achar, M. Nakhla and Q. Zhang, "Full-wave analysis of high-speed interconnects using complex frequency hopping", IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 17, pp. 997 - 1016, Oct. 1998.

92. M. Kolbehdari, M. Srinivasan, M. Nakhla, Q. Zhang and R. Achar, "Simultaneous time and frequency domain solution of EM problems using finite element and CFH techniques", IEEE Transactions on Microwave Theory and Techniques, vol. 44, no. 9, pp. 1526-1534, Sept. 1996.

Chapters in Books

91. B. Nouri, E. Gad, M. Nakhla and R. Achar, Model Order Reduction in Microelectronics, Chapter XX: Handbook on Model Order Reduction, Walter De Gruyter GmbH, Berlin, Germany, 2019

92. E. Gad, M. Nakhla and R. Achar, Model Order Reduction of High-Speed Interconnects using Integrated Congruence Transform, Chapter XVII: Model Order Reduction: Theory, Research Aspects and Applications, Springer, Heidelberg, Germany, 2007.

93. M. Nakhla and R. Achar, Recent Advances in Interconnect Modeling and Simulation of High-Speed Interconnects, Chapter VII: Computational Methods in Large Scale simulation, National University of Singapore (ed.), World Scientific Publishing Co. Pte. Ltd. 2005.

94. M. Nakhla and R. Achar, Interconnect Modeling and Simulation, Chapter XVII: The VLSI Handbook, pp. 17.1 - 17.29, Boca Raton: CRC Press, 2000.

95. R. Achar and M. Nakhla, Minimum Realization of Reduced-Order Models of High-Speed Interconnect Macromodels, Chapter III: Signal Propagation on Interconnects, pp. 23-45, Boston: Kluwer Academic Publishers, 1998.

96. M. Nakhla, R. Achar and R. Khazaka, Modeling and Simulation of High-Speed VLSI Interconnects, Chapter IV: Circuits And Systems In The Information Age, pp. 187 - 216, NJ: IEEE Publishers, 1997.

Refereed International Conferences

97. A. Javaid, R. Achar and J. Tripathi, "Efficient Modeling of Random Jitter Due to Stochastic Power Supply Noise in CMOS Inverters", Proc. 31st IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, Accepted for publication, pp. 1-3, Oct. 2022, San Jose, USA.

98. A. Javaid, R. Achar and J. Tripathi, "Estimation of PSIJ in CMOS Inverters via Knowledge Based Artificial Neural Networks", Proc. 2022 IEEE Conference on Signal and Power Integrity (SPI), pp. 1-3, May 2022, Sigen, Germany.

99. D. Singh, J. Tripathi and R. Achar, "Modeling Power Supply Induced Jitter in a Voltage-Mode Driver with Long Transmission Lines", Proc. IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), pp. 1-4, May 2021, Cali, Columbia.

100. I. Erdin and R. Achar, "Fast Power Integrity Analysis of PDNs with Arbitrarily Shaped Power-Ground Plane Pairs", Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 1-3, Dec. 2020, Shenzhen, China.

101. R. Kumar, S. Likith, S. Kumar, S. Roy, B. Kaushik, R. Achar and R. Sharma, "Estimating Per-Unit-Length Resistance Parameter in Emerging Copper-Graphene Hybrid Interconnects via Prior Knowledge based Accelerated Neural Networks", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct. 2020, San Jose, CA.

102. I. Erdin and R. Achar, "Gauss-Newton Method for Performance Evaluation of Decoupling Capacitors on Resonant Parallel Plates", Proc. 29th IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct. 2020, San Jose, CA (Best Conference Paper Award).

103. I. Erdin and R. Achar, "On the Effectiveness Range of Decoupling Capacitors Including Mutual Coupling", Proc. 2020 IEEE Conference on Signal and Power Integrity (SPI), pp. 1-3, May 2020, Cologne, Germany.

104. R. Kumar, A. Kumar, S. Guglani, S. Kumar, S. Roy, B. Kaushik, R. Sharma and R. Achar, "Temperature-Aware Compact Modeling for Resistivity in Ultra-Scaled Cu-Graphene Hybrid Interconnects", Proc. 2020 IEEE Conference on Signal and Power Integrity (SPI), pp. 1-3, May 2020, Cologne, Germany.

105. S. Ganeshan, N. Kumar and R. Achar, "A Comparative Study of MAGMA and cuBLAS Libraries for GPU based Vector Fitting", Proc. IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), pp. 1-4, Feb. 2020, San Jose, Costarica.

106. S. Guglani, A. Kumar, R. Kumar, B. K. Kaushik, R. Sharma, R. Achar and S. Roy, "Temperature-Aware Closed-Form Matrix Rational Approximation Model for Crosstalk Analysis of Multi-Walled Carbon Nanotube Interconnects, Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 1-3, Dec. 2019, Xinxing District, Taiwan.

107. N. Kumar, S. Ganeshan and R. Achar, "GVF: GPU based Vector Fitting", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, pp. 1-3, Oct. 2019, Montreal, Canada.

108. A. Kumar, B. K. Kaushik, S. Roy and R. Achar, "Crosstalk Analysis in MWCNTs using a Closed-Form Matrix Rational Approximation Technique", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, pp. 1-3, Oct. 2019, Montreal, Canada.

109. A. Bal, J. Tiwari, J. Tripathi and R. Achar, "A Novel Programmable Delay Line for VLSI Systems", IEEE 23rd Workshop on Signal and Power Integrity (SPI), pp. 1-3, June 2019, Chambery, France.

110. M. Illikkal, J. Tripathi, H. Shrimali and R. Achar, "Analysis of Jitter for a Chain-of-Inverters including On-chip Interconnects", IEEE 23rd Workshop on Signal and Power Integrity (SPI), pp. 1-3, June 2019, Chambery, France.

111. I. Erdin and R. Achar, "Multipin Optimization of Decoupling Capacitors on Segmented Resonant Planes", IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), pp. 1-3, June 2019, Boston, MA.

112. I. Erdin and R. Achar, "A Generalized Segmentation Algorithm for Planar Resonant Structures with Discrete Components", Proc. IEEE MTT-S International Microwave Symposium (IMS), pp. 31-34, June 2019, Boston, MA.

113. I. Erdin and R. Achar, "A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures," IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), pp. 25-28, Feb. 2019.

114. I. Erdin and R. Achar, "Multi-pin Optimization of Decoupling Capacitors on Practical Printed Circuit Boards", IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 1-3, Dec. 2018, Chandigarh, India.

115. I. Erdin and R. Achar, "Analytical Modeling of Power Pin Impedance in Parallel Power & Ground Planes", IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), pp. 1-3, Iceland, Aug. 2018.

116. J. Tripathi, A. Jain, M. Marinkovic and R. Achar, "Analysis of PSIJ in the presence of both ground-bounce and transmission media", IEEE 22nd Workshop on Signal and Power Integrity (SPI), pp. 1-3, May 2018, Brest, France.

117. I. Erdin and R. Achar, "Placement of decoupling capacitors on power transmission lines", IEEE Intl. Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC)", pp. 152-154, May 2018, Singapore.

118. I. Erdin and R. Achar, "Analysis of Decoupling Capacitors Inside Via Arrays with Mutual Interaction", Proc. 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 1-3, Dec. 2017, Haining, China.

119. J. Tripathi and R. Achar, "Modeling the effects of Transmission Media on Power Supply Induced Jitter". Proc. 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 1-3, Dec. 2017, Haining, China.

120. Y. Tao, B. Nouri, E. Gad, M. Nakhla, Q. Sun and R. Achar, "MIP: Moment-based interpolation projection for parameterized reduced models of the DC operating point in nonlinear circuits", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, Oct. 2017, San Jose, USA.

121. I. Erdin and R. Achar, "Analysis of Pin-to-Capacitor Spacing in Power Delivery Networks Designed as Parallel-Plate Power-Ground Pairs", Proc. 2017 IEEE Conference on Signal and Power Integrity (SPI), pp. 1-3, May 2017, Baveno, Italy.

122. Y. Tao, K. Guo, F. Ferranti, B. Nouri, M. Nakhla and R. Achar, "Time-Domain Variability Analysis of Large Circuits with Stochastic Linear Terminations", Proc. 2017 IEEE Conference on Signal and Power Integrity (SPI), pp. 1-3, May 2017, Baveno, Italy.

123. I. Erdin and R. Achar, “Pin-Capacitor Spacing as a Design Guide to Power Delivery Networks”, Proc. IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), pp. 70-72, May 2017, Sevilla, Spain.

124. I. Erdin R. Achar, and K. Erdin, "Closed-Form Small Signal Model of A Buck Controller Including Power Transmission Lines", Proc. 2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 1-3, Dec. 2016, Honolulu, USA.

125. I. Erdin, and R. Achar, "Addressing Planar Noise Coupling in Multilayer PCB Structures", Proc. International Symposium on Electromagnetic Compatibility, pp. 189-190, July 2016, Ottawa, ON, Canada.

126. Y. Tao, M. Farhan, B. Nouri, M. Nakhla and R. Achar, "Efficient variability analysis using parameterized model-order reduction", Proc. 2016 IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, May 2016, San Fransciso, USA

127. I. Erdin and R. Achar, "Small Signal AC Analysis of Controller Circuits with Distributed PCB Effects", Proc. IEEE Asia Pacific International Symposium on Electromagnetic Compatibility, pp. 1150-1152, May 2016, Shenzen, China.

128. I. Erdin and R. Achar, "Addressing PCB effects in the design of a buck converter", Proc. 20th IEEE Conference on Signal and Power Integrity (SPI), pp. 1-3, May 2016, Torino, Italy.

129. Y. Tao, B. Nouri, M. Nakhla and R. Achar, "Efficient time-domain variability analysis using parameterized model-order reduction", Proc. 20th IEEE Conference on Signal and Power Integrity (SPI), pp. 1-4, May 2016, Torino, Italy.

130. I. Erdin and R. Achar, "Characteristic Impedance of Asymmetrical Differential Traces: Closed-Form Relations for Signal Integrity Analysis". Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 43-45, Dec. 2015, Seoul, South Korea.

131. B. Nouri, M. Nakhla and R. Achar, “A novel algorithm for efficient simulation of nonlinear transmission lines for RF applications via model order reduction”, Proc. IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), pp. 1-3, Aug. 2015, Ottawa, ON, Canada.

132. S. Nabavi, E. Gad, M. Nakhla and R. Achar, “Statistical analysis of intermodulation distortion in RF circuits using decoupled polynomial chaos”, Proc. IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), pp. 1-3, Aug. 2015, Ottawa, ON, Canada.

133. M. Farhan, E. Gad, M. Nakhla and R. Achar, "High Order Envelope Following Method for Parallel Simulation of Power Converter Circuits", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging and Systems, pp. 77-80, Oct. 2014, Portland, OR, USA

134. M. Farhan, E. Gad, M. Nakhla and R. Achar, "High-Order Envelope Following Method for Accurate Transient Analysis of Almost Periodic Electrical Circuits", Proc. IEEE International Microwave Symposium, pp. 1-3, June 2014, Tampa, FL, USA.

135. S. Nabavi, E. Gad, M. Nakhla and R. Achar, "Efficient statistical analysis of microwave circuits using decoupled polynomial chaos", Proc. IEEE International Microwave Symposium, pp. 1-3, June 2014, Tampa, FL, USA.

136. M. Rufuie, E. Gad, M. Nakhla, R. Achar and M. Farhan, "Fast Variability Analysis of General Nonlinear Circuits Using Decoupled Polynomial Chaos", Accepted for publication in Proc. 18th IEEE Workshop on Signal and Power Integrity (SPI), May 2014, Ghent, Belgium.

137. B. Nouri, M. Nakhla and R. Achar, "A Novel Algorithm for Optimum Order Estimation of Nonlinear Reduced Macromodels", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 137-140, Oct. 2013, San Jose, USA.

138. T. Pham, E. Gad, M. Nakhla and R. Achar, "Efficient Hermite-based Variability Analysis using Approximate Decoupling Technique", Proc. 17th IEEE Workshop on Signal and Power Integrity (SPI), pp. 119-122, May 2013, Paris, France.

139. D. Paul, R. Achar, M. Nakhla and N. Nakhla, "Efficient Parallel Scheduler for Circuit Simulation Exploiting Binary Link Formulations", Proc. IEEE International Conference on Latin American Circuits and Systems, pp. 1-4, Feb. 2013, Lima, Peru.

140. M. Farhan, E. Gad, M. Nakhla and R. Achar, "An Efficient Method for Transient Simulation of High-Speed Interconnects with Nonlinear Terminations", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 119-122, Oct. 2012, Phoenix, USA.

141. M. Kabir, R. Khazaka, R. Achar and M. Nakhla, "Loewner-Matrix Based Efficient Algorithm for Frequency Sweep of High-Speed Modules", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 185-189, Oct. 2012, Phoenix, USA.

142. M. Farhan, E. Gad, M. Nakhla and R. Achar, "Efficient Transient Simulation of Transmission Lines and Distributed Circuits Using High-Order Stable Methods", Proc. IEEE International Microwave Symposium, pp. 1-3, June 2012, Montreal, Canada.

143. M. Farhan, E. Gad, M. Nakhla and R. Achar, "A Multi-Core High-Order A-Stable and L-Stable Integration Method for Fast Transient Simulation of High-Speed Interconnect and Transmission Line Circuits, Proc. 16th IEEE Workshop on Signal and Power Integrity (SPI), pp. 89-92, May 2012, Sorrento, Italy.

144. M. Farhan, N. Nakhla, M. Nakhla, R. Achar and A. Ruehli, "Waveform Relaxation and Overlapping Partitioning Techniques for Tightly Coupled Interconnects", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 111-114, Oct. 2011, San Jose, CA, USA.

145. A. Charest, M. Nakhla and R. Achar, "Passive Model-Order Reduction of RLC Circuits with Embedded Time-Delay Descriptor Systems", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 223-226, Oct. 2011, San Jose, CA, USA.

146. B. Nouri, M. Nakhla and R. Achar, "A Novel Algorithm for Optimum Order Estimation of Reduced Order Macromodels", Proc. 15th IEEE Workshop on Signal Propagation on Interconnects, pp. 33-36, May 2011, Naples, Italy (* BEST PAPER AWARD *).

147. A. Saini, M. Nakhla and R. Achar, "Time-Domain Adjoint Sensitivity of High-Speed Interconnects", Accepted for publication in Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 153-156, Oct. 2010, Austin, TX, USA.

148. B. Nouri, M. Nakhla and R. Achar, "A Novel Clustering Scheme for Reduced-Order Macromodeling of Massively Coupled Interconnect Structures", Accepted for publication in Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 77-80, Oct. 2010, Austin, TX, USA.

149. A. Charest, M. Nakhla and R. Achar, "Efficient passivity verification of delayed rational function macromodels from networks characterized by tabulated data ", Proc. 14th IEEE Workshop on Signal Propagation on Interconnects, pp. 109-112, May 2010, Hildesheim, Germany.

150. A. Narayanan, R. Achar, N. Nakhla and M. Nakhla, "Fast EMI Analysis of Massively Coupled Interconnects with Long Delay", Proc. IEEE Asia Pacific International Symposium on Electromagnetic Compatibility, pp. 618-621, April 2010, Beijing, China ( *BEST STUDENT PAPER AWARD *).

151. H. Dhindsa, N. Nakhla, R. Achar, M. Nakhla, D. Paul and A. Sridhar, "A Parallel Framework for Transient Power Integrity Analysis", Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Dec. 2009, HongKong (*INVITED PAPER).

152. A. Charest, M. Nakhla and R. Achar, "Passivity Verification and Enforcement of Delayed Rational Approximations from Scattering Parameter Based Tabulated Data", Proc. IEEE International Conference on Electrical Performance of Electronic Packaging, pp. 65-68, Oct. 2009, Portland, OR, USA..

153. R. Achar, M. Nakhla, A. Sridhar, H. Dhindsa and D. Paul, "Power Distribution Networks using Waveform Relaxation", Proc. 13th IEEE Workshop on Signal Propagation on Interconnects, pp. 1-4, May 2009, Strasbourg, France, May. 2009.

154. A. Charest, M. Nakhla and R. Achar, "Passivity Verification and Enforcement of Delayed Rational Function Macromodels from Networks Characterized by Tabulated Data", Proc. 13th IEEE Workshop on Signal Propagation on Interconnects, pp. 1-4, May 2009, Strasbourg, France, May. 2009.

155. H. Dhindsa, A. Sridhar, R. Achar, M. Nakhla and D. Paul, "Transient Analysis of Power Grid Networks via Waveform Relaxation Techniques", International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects (IWMS), pp. 91-94, Feb. 2009, (*INVITED PAPER).

156. D. Paul, N. Nakhla, R. Achar, and M. Nakhla, "Coupled high-speed interconnect analysis on parallel platforms", Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 202 - 205, Dec. 2008, Seoul, Korea (*INVITED PAPER).

157. D. Paul, N. Nakhla, R. Achar, and M. Nakhla, "Parallel algorithm for analysis of high-speed interconnects", Proc. IEEE 17th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 191-195, Oct. 2008, San Jose, CA, USA.

158. N. Soveiko, M. Nakhla, R. Achar and E. Gad, "Scalable parallel matrix solver for steady state analysis of large nonlinear circuits", IEEE International Microwave Symposium Digest, pp. 1401-1404, June 2008, Atlanta, GA, USA.

159. C. Walkey, D. Paul, M. Nakhla and R. Achar, "A novel passivity verification and enforcement algorithm for macromodels of microwave devices", IEEE International Microwave Symposium Digest, pp. 611-614, June 2008, Atlanta, GA, USA.

160. R. Achar, A. Sridhar, N. Nakhla and M. Nakhla, "Parallel EMI analysis of large coupled interconnects via transverse partitioning and waveform relaxation", Proc. Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008. pp. 490-493, May 2008, Singapore (*INVITED PAPER).

161. B. Nouri, R. Achar, M. Nakhla and D. Saraswat, "z-Domain Orthonormal Vector Fitting for Macromodeling High-Speed Modules Characterized by Tabulated Data", Proc. 12th IEEE Workshop on Signal Propagation on Interconnects, pp. 1-4, May 2008, Germany.

162. A. Sridhar, N. Nakhla, R. Achar and M. Nakhla, "Fast EMC Analysis of high-speed interconnects via Waveform Relaxation and Transverse Partitioning", Proc. IEEE Conf. on Electrical Performance of Electronic Packaging, pp. 329-332, Oct. 2007, Atlanta, GA, USA.

163. N. Nakhla, M. Nakhla, R. Achar and A. Ruehli, "Parallel Simulation of High-Speed Interconnects using Delay Extraction and Transverse Partitioning", Proc. IEEE Conf. on Electrical Performance of Electronic Packaging, pp. 237-240, Oct. 2007, Atlanta, GA, USA.

164. N. Nakhla, M. Nakhla, and R. Achar, "Sparse and Passive Reduction of Massively Coupled Large Multiport Interconnects", Proc. ICCAD, pp. 622-626, Nov. 2007, San Jose, CA.

165. C. Chen, D. Saraswat, E. Gad, M. Nakhla, R. Achar and M. C. E. Yagoub, "Passivity Enforcement for Method of Characteristics-based Macromodels", Proc. International Symposium on Signals, Systems and Electronics (ISSSE), pp. 25-28, July 2007, Montreal, Canada.

166. C. Walkey, D. Paul, M. Nakhla and R. Achar, "Efficient Passive Macromodelling of High-Speed Interconnect", Proc. International Symposium on Signals, Systems and Electronics (ISSSE), pp. 275-278, July 2007, Montreal, Canada.

167. L. Filipovic, R. Achar and M. Nakhla, "Fast Algorithm for Transient Analysis of Distributed Interconnects Including Driver and Load", Proc. IEEE International North Eastern Circuits and Systems Conference, pp. 1413-1416, July 2007, Montreal, Canada.

168. A. Charest, M. Nakhla, and R. Achar, "Passive Macromodeling of Transmission Line Type Interconnects Characterized by Tabulated Data", Proc. IEEE International North Eastern Circuits and Systems Conference, pp. 142-1424, July 2007, Montreal, Canada.

169. C. Chen, E. Gad, M. Nakhla and R. Achar, "Model-Order Reduction of Frequency-Dependent Interconnects Based on Integrated Congruence Transform", Proc. IEEE International North Eastern Circuits and Systems Conference, pp. 1429-1432, July 2007, Montreal, Canada.

170. N. Nakhla, M. Nakhla and R. Achar, "Model Order Reduction of Large Multiport Interconnect Structures using Waveform Relaxation Techniques", Proc. 11th IEEE Workshop on Signal Propagation on Interconnects, pp. 69-60, May 2007, Germany.

171. E. Gad, M. Nakhla, R. Achar and Y. Zhou, "An Absolutely-Stable Arbitrarily high-order Implicit Numerical Integration Method and its application to the Time-Domain Simulation of Interconnect Circuits", Proc. 11th IEEE Workshop on Signal Propagation on Interconnects, pp. 186-187, May 2007, Germany.

172. D. Paul, M. Nakhla, R. Achar and A. Weisshaar, "A passive algorithm for modeling frequency-dependent parameters of coupled interconnects", Proc. IEEE 15th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 185-188, Oct. 2006, Scottsdale, AZ (Best Student Paper Award).

173. N. Nakhla, M. Nakhla, and R. Achar, "A General Approach for Time-Domain Sensitivity Analysis of High-Speed Interconnects", Proc. IEEE 15th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 189-192, Oct. 2006, Scottsdale, AZ.

174. G. Shinh, N. Nakhla, R. Achar, M. Nakhla, A. Dounavis and I. Erdin, "Fast EMC analysis of high-speed interconnects with frequency-dependent parameters", Proc. IEEE International Symposium on Electromagnetic Compatibility, pp. 14-18, Aug. 2006, Portland, OR.

175. D. Paul, M. Nakhla, R. Achar, A. Weisshaar, "An Automated Algorithm for Broadband Modeling of High-Frequency Microwave Devices", Proc. IEEE International Microwave Symposium, pp. 1767-1770, June 2006, San Francisco, CA.

176. D. Paul, M. Nakhla, R. Achar, A. Weisshaar, "Broadband Macromodeling of High-Speed Passive Modules", Proc. 10th IEEE Workshop on Signal Propagation on Interconnects, May 2006, Berlin, Germany.

177. C. Chen, E. Gad, W. Tseng, M. Nakhla and R. Achar, "A Passive Model-Order Reduction Algorithm for RLC Networks with Embedded Delay Elements", Proc. 10th IEEE Workshop on Signal Propagation on Interconnects, May 2006, Berlin, Germany.

178. D. Saraswat, R. Achar and M. Nakhla, "Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters", Proc.VLSI Design, pp. 667 - 671 , Jan. 2006, Hyderabad, India.

179. G. Shinh, N. Nakhla, R. Achar, M. Nakhla and I. Erdin, "Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks", Proc. VLSI Design, pp. 672-676, Jan. 2006, Hyderabad, India.

180. N. Nakhla, A. Ruehli, M. Nakhla, R. Achar and C. Chen, "Waveform relaxation techniques for simulation of coupled interconnects with frequency-dependent parameters", Proc. IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 47-50, Oct. 2005, Austin, Texas.

181. D. Saraswat, R. Achar and M. Nakhla, "Restoration of Passivity in S-parameter Data of Microwave Measurements", IEEE International Microwave Symposium (IMS) Digest, pp. 1131 - 1134, June 2005, Long Beach, CA.

182. G. Shinh, N. Nakhla, R. Achar, M. Nakhla, and I. Erdin, "Analysis of Multiconductor Transmission Lines with Frequency-Dependent Parameters and Incident Electromagnetic Fields," IEEE International Microwave Symposium (IMS) Digest, pp. 1107 - 1110, June 2005, Long Beach, CA.

183. N. Nakhla, A. Dounavis, M. Nakhla and R. Achar, "Delay-extraction based sensitivity analysis of multiconductor transmission lines with nonlinear terminations," Proc. IEEE International Microwave Symposium, pp. 3520 - 3530, June 2005, Long Beach, CA.

184. E. Gad, C. Chen, M. Nakhla, and R. Achar, "Passivity Verification in Delay-Based Macromodels of Electrical Interconnects", Proc. 9th IEEE Workshop on Signal Propagation on Interconnects, pp. 125-128, May 2005, Garmisch-Partenkirchen, Germany.

185. D. Saraswat, R. Achar and M. Nakhla, "On passivity enforcement for macromodels of S-parameter based tabulated subnetworks", Proc. IEEE International Conference on Circuits and Systems, pp. 3777-3780, May 2005, Kobe, Japan.

186. N. Nakhla, R. Achar and M. Nakhla, "Closed-form compact SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters", Proc. IEEE International Conference on Circuits and Systems, pp. 5770-5773, May 2005, Kobe, Japan

187. D. Saraswat, R. Achar and M. Nakhla, "Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects", Proc. IEEE International Conference on VLSI Design, pp. 629-633, January 2005, Kolkata, India.

188. N. Nakhla, R. Achar and M. Nakhla, "Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects", Proc. IEEE Asia South Pacific Design Automation Conference, pp. 1082-1085, Jan. 2005, Shanghai, China.

189. D. Saraswat, R. Achar, M. Nakhla, and R. Khazaka, "Passive Complex Frequency Hopping for Compact Macromodeling of Microwave Subnetworks", Proc. IEEE Asia Pacific Microwave Conference, pp. 84-85, December 2004, New Delhi, India.

190. N. Nakhla, A. Ruehli, M. Nakhla, and R. Achar, "Simulation of Coupled Interconnects using Waveform Relaxation and Transverse Partitioning", Proc. IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 25-28, Oct. 2004, Portland, Oregon (IBM Best Student Paper Award).

191. G. Shinh, N. Nakhla, R. Achar, M. Nakhla, A. Dounavis, and I. Erdin, "Efficient SPICE Macromodel for EMI Analysis of Electronic Packages and High-Speed Interconnects", Proc. IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 277-280, Oct. 2004, Portland, Oregon.

192. D. Saraswat, R. Achar and M. Nakhla, "A methodology for generating compact macromodels for high-frequency interconnect and microwave subnetworks", IEEE International Microwave Symposium (IMS) Digest, pp. 707-710, June 2004, Fort Worth, USA.

193. P. Pai, E. Gad, R. Achar, R. Khazaka and M. Nakhla, "Parametric Circuit Reduction for Steady-State Simulation with multi-tone Inputs", IEEE International Microwave Symposium (IMS) Digest, pp. 937-940, June 2004, Fort Worth, USA.

194. D. Saraswat, R. Achar and M. Nakhla, "Circuit Simulation of S-parameter based Interconnects via Passive Macromodels", Proc. IEEE International Northeast Workshop on Circuits and Systems, pp. 309-312, June 2004, Montreal, Canada.

195. N. Nakhla, A. Dounavis, R. Achar and M. Nakhla, "Passive Macromodeling and Sensitivity Analysis of Multiconductor Transmission Lines", Proc. IEEE International Northeast Workshop on Circuits and Systems, pp. 33-36, June 2004, Montreal, Canada.

196. G. Shinh, N. Nakhla, R. Achar, M, Nakhla, I. Erdin and A. Dounavis, "Fast Transient Analysis Of Incident Field Coupling To Multiconductor Transmission Lines", Proc. 10th International Symposium on Antenna Technology and Applied Electromagnetics and URSI Conference, pp. 281-284, July 2004, Ottawa, Canada.

197. D. Saraswat, R. Achar and M. Nakhla, "Time-domain passive macromodels of S-parameter based EM subnetworks", Proc. 10th International Symposium on Antenna Technology and Applied Electromagnetics and URSI Conference, pp. 357-360, July 2004, Ottawa, Canada.

198. N. Nakhla, A. Dounavis, R. Achar and M. Nakhla, "Fast Sensitivity Analysis of Transmission Line Networks", Proc. IEEE International Symposium on Circuits and Systems (ISCAS) - pp. V121-V124, May 2004, Vancouver, Canada.

199. P. Pai, E. Gad, R. Achar, R. Khazaka and M. Nakhla, "Circuit Reduction For Computing Large-change Sensitivity of Steady-state Operating Point", Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. V333-V335, May 2004, Vancouver, Canada.

200. D. Saraswat, R. Achar and M. Nakhla, "A Fast Algorithm for Near Optimal Passive Reduction of High-Speed Interconnect Networks", Proc. 8th IEEE Workshop on Signal Propagation on Interconnects, pp.91-94, May 2004, Heidelberg, Germany.

201. P. Pai, E. Gad, R. Achar, and M. Nakhla, "Analysis of Frequency Dependent Transmission Lines Using Integrated Congruence Transform", Proc. IEEE International Symposium Applied Computational Electromagnetics (ACES), pp. 5.1.1-5.1.4, Apr 2004, Syracuse, Canada.

202. N. Nakhla, A. Dounavis, R. Achar and M. Nakhla, "Preserving Passivity and Causality in Transmission Lines Macromodels", Proc. IEEE International workshop on Progress in Electromagnetics Research Symposium (PIERS), pp. 429-433, April 2004, Pisa, Italy.

203. D. Saraswat, R. Achar and M. Nakhla, "Enforcing Passivity for Rational function Based Macromodels of Tabulated Data", Proc. IEEE 12th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP 2003), pp. 251-254, Oct. 2003, Princeton, NJ.

204. A. Dounavis, N. Nakhla, R. Achar and M. Nakhla, "Delay Extraction and Passive Macromodeling of Lossy Coupled Transmission Lines", Proc. IEEE 12th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 295-298, Oct. 2003, Princeton, NJ (Best Student Paper Award).

205. D. Saraswat, R. Achar and M. Nakhla, "Passive Macromodeling Of High-speed Packaging Subnetworks Characterized by Measured/Simulated Data", Proc. IEEE International workshop on Progress in Electromagnetics Research Symposium (PIERS), Oct. 2003, Hawaii, USA (** INVITED PAPER **).

206. D. Saraswat, R. Achar and M. Nakhla, "Passive Macromodels of Microwave Subnetworks Characterized by Measured/Simulated Data", IEEE International Microwave Symposium (IMS) Digest, pp. 999-1002, June 2003, Philadelphia, PA - (3rd Best Student Paper Award).

207. D. Saraswat, R. Achar and M. Nakhla, "Passive macromodeling of subnetworks characterized by measured data", Proc. IEEE International Symposium on Circuits and systems, ISCAS, pp. 502-505, June, 2003, Bangkok, Thailand (** INVITED PAPER **).

208. D. Saraswat, R. Achar and M. Nakhla, "On Passivity Check and Compensation of Macromodels from Tabulated Data", Proc. 7th IEEE Workshop on Signal Propagation on Interconnects, pp. 25-28, May 2003, Siena, Italy.

209. D. Saraswat, R. Achar and M. Nakhla, "A Fast Algorithm and Practical Considerations for Passive Macromodeling of Measured/Simulated Data," Proc. IEEE 11th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 297-300, Oct. 2002, Monterey, CA - (Best Student Paper Award).

210. I. M. Elfadel, A. Dounavis, H-M. Huang, M. Nakhla, A. E. Ruehli and R. Achar, "Accuracy and Performance of Passive Transmission Line Macromodels Based on Optimal Matrix Rational Approximations," Proc. IEEE 11th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp 351-354., Oct. 2002, Monterey, CA.

211. A. Dounavis, I. M. Elfadel, R. Achar, M. Nakhla, A. E. Ruehli and H-M. Huang, "Lossy Transmission Line Passive Macromodeling Algorithm - Three Case Studies," Proc. IEEE 11th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp 355-358, Oct. 2002, Monterey, CA.

212. A. Dounavis, R. Achar and M. Nakhla, "On passive time-domain macromodels of distributed transmission line networks," IEEE International Microwave Symposium (IMS) Digest, vol. 2, pp. 975-978, June 2002, Seattle, Washington.

213. A. Dounavis, R. Achar and M. Nakhla, "Passive closed-form time-domain macromodels for on-chip distributed RC interconnects," Proc. IEEE Custom Integrated Circuits Conference, pp. 509-512, May 2002, Orlando, FL.

214. P. Gunupudi, R. Khazaka, A. Dounavis, R. Achar and M. Nakhla, "Global multi-level reduction technique for nonlinear simulation of high-speed interconnects," Proc. IEEE Electrical Performance of Electronic Packaging (EPEP), pp. 259 -262, Oct. 2001, Cambridge, MA (Best Student Paper Award).

215. A. Dounavis, R. Achar and M. Nakhla, "A General Class of Passive Macromodels for Efficient Sensitivity Analysis of High-Speed Distributed Interconnects with Nonlinear Terminations," Proc. IEEE international Conference on Electronics, Circuits Systems, pp. 899-902, Malta, Sept. 2001.

216. A. Dounavis, R. Achar and M. Nakhla, "Passive Macromodels For Distributed High Speed Interconnects", Proc. IEEE European Conference on Circuits Theory and Design (ECCTD), pp. S18.4.1-S18.4.4, August. 2001, Espoo, Finland.

217. I. Erdin, A. Dounavis, R. Achar, M. Nakhla, "Circuit Simulation of Incident Field Coupling to Multiconductor Transmission Lines with Frequency-Dependent Losses," Proc. IEEE EMC International Symposium, pp. 1084-1087, Aug. 2001, Montreal, CA.

218. A. Dounavis, R. Achar and M. Nakhla, "Efficient Sensitivity Analysis of Lossy Multiconductor Transmission Lines with Nonlinear Terminations," IEEE MTT-S International Microwave Symposium (IMS) Digest, pp. 2099-2102, June 2001, Phoenix, AZ.

219. A. Dounavis, P. K. Gunupudi, E. Gad, R. Khazaka, R. Griffith, R. Achar and M. Nakhla, "Addressing Transient Analysis of Multiport Distributed Interconnects," 9th Topical meeting on Electrical Performance of Electronic Packaging, pp. 243-246, Oct. 2000, Phoenix, AZ.

220. M. Nakhla and R. Achar, "Managing complexity in high-speed VLSI circuits using model-reduction techniques", SSGRR-2000, Aug. 2000, L'Aquila, Italy (Invited Paper).

221. A. Dounavis, E. Gad, R. Achar and M. Nakhla, "Passive Model-Reduction of Distributed Networks with Frequency-Dependent Parameters," IEEE MTT-S International Microwave Symposium Digest, vol 3, pp 1789-1792, June 2000, Boston, MA.

222. E. Gad, A. Dounavis, M. Nakhla and R. Achar, "Passive Model Order Reduction of Multiport Distributed Interconnects," Proc. IEEE Design Automation Conference, vol. 37, pp 526-531, June 2000, Los Angeles, CA.

223. A. Dounavis, E. Gad, R. Achar and M. Nakhla, "Passive Model-reduction of distributed networks including frequency-dependent parameters", Proc. 4th IEEE International Workshop on Signal Propagation on Interconnects, pp. 1.1.1-1.1.2, May 2000, Hannover, Germany.

224. P. Gunupudi, R. Achar, M. Nakhla and A. Dounavis, "Simulation of distributed interconnects with frequency dependent parameters using krylov-space techniques", Proc. IEEE European Conference on Circuits Theory & Design (ECCTD), pp. 425-428, Sept. 99, Stresa, Italy (** INVITED PAPER **).

225. M. Nakhla, R. Achar and P. Gunupudi, "Simulation of high-speed interconnects using multi-level model-reduction techniques", Proc. 1999 IEEE International Manufacturing and Packaging Symposium (IMAPS), July 1999, Ojai, CA (** INVITED PAPER **).

226. R. Achar and M. Nakhla, "Efficient Simulation of on-chip RF components using model-reduction techniques", Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 81-84, June 1999, Orlando, FL.

227. A. Dounavis, X. Li, M. Nakhla and R. Achar, "Passive closed-loop transmission line model for general purpose circuit simulators," IEEE International Microwave Symposium Digest, pp. 377-380, June 1999, Los Angeles, CA.

228. P. Gunupudi, M. Nakhla and R. Achar, "Multipoint Multiport Reduction of High-Speed Distributed Interconnects Using Krylov-Space Techniques", Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 242-245, June 999, Orlando, FL.

229. R. Achar, P. Gunupudi and M. Nakhla, "Multilevel Multipoint Model-Reduction Algorithm for Macromodeling of Multiport Distributed Networks", Proc. 3rd IEEE International Workshop on Signal Propagation on Interconnects, pp. 1.2.1-1.2.2, May 1999, Hannover, Germany.

230. R. Achar and M. Nakhla, "Recent advances in simulation and modeling of high-speed interconnections", Proc. 12th International Workshop on circuits and Systems, April, 1999, Karuizawa, Japan (** INVITED PAPER **).

231. P. Gunupudi, M. Nakhla and R. Achar, "Efficient simulation of high-Speed distributed interconnects using Krylov-space techniques", Proc. IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 295-298, Oct. 98, New York, USA (Best Student Paper award).

232. R, Achar and M. Nakhla, "A novel technique for minimum-order macromodel synthesis of high-speed interconnect subnetworks", Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 70 - 73. June, 1998, Monterey, CA.

233. R. Achar, M. Nakhla and E. Ahmed "Nonlinear transient simulation of embedded subnetworks characterized by s-parameters using complex frequency hopping", IEEE MTT-S International Microwave Symposium Digest, pp. 1219 - 1223, June 1998, Baltimore, USA.

234. X. Li, M. Nakhla and R, Achar, "A universal closed-loop high-speed interconnect model for general purpose circuit simulators", Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 66 - 69, June, 1998, Monterey, CA.

235. R. Achar and M. Nakhla, "Addressing passivity issues in CFH", Proc. 2nd IEEE International Workshop on Signal Propagation on Interconnects, pp 33-34, May 1998, Hannover, Germany.

236. R. Achar and M. Nakhla, "A fast method for nonlinear simulation of transmission line networks", Proc. IEEE International Symposium on Nonlinear Theory and Its Applications (NOLTA), pp. 837-840, Nov. 1997, Hawaii, USA (** INVITED PAPER **).

237. R. Achar, M. Nakhla and E. Chiprout, "Block CFH: A model-reduction technique for distributed interconnect networks", Proc. IEEE European Conference on Circuits Theory and Design (ECCTD), pp. 396-401, Sept. 1997, Budapest, Hungary (** INVITED PAPER **).

238. R. Achar, M. Kolbehdari and M. Nakhla, "A unified approach for mixed EM/circuit simulation using model-reduction techniques", IEEE MTT-S International Microwave Symposium Digest, June 1997, pp. 1017-1021, Denver, USA.

239. M. Nakhla, R. Khazaka and R. Achar, "A universal macromodeling technique for high-speed VLSI interconnects", Proc. 1st IEEE International Workshop on Signal Propagation on Interconnects, pp. 5.1.1-5.1.2, May 1997 Hannover, Germany, (** INVITED PAPER **).

240. M. Kolbehdari, M. Nakhla, R. Achar and M. Srinivasan, "Solution of EM problems using reduced-order models by complex frequency hopping", Proc. 13th IEEE Annual Review of Progress in Applied Computational Electromagnetics, March, 1997 Monterey, California.

241. G. Zheng, Q. J. Zhang, M. Nakhla and R. Achar "An efficient approach for simulation of measured subnetworks with complex frequency hopping", Proc. IEEE/ACM Int. Conf. Computer Aided Design (ICCAD), pp. 23-26, Nov 1996, San Jose, CA, USA.

242. R. Achar, M. Nakhla and Q. J. Zhang, "Addressing high-frequency issues in VLSI interconnects with full-wave models and CFH", Proc. IEEE/ACM Int. conference on Computer Aided Design (ICCAD), pp. 53-57, Nov. 1995, San Jose, CA, USA.

243. M. Nakhla, E. Chiprout, R. Achar and R. Khazaka, "Recent progress in simulation of high speed interconnects using moment matching techniques", Proc. IEEE 4th Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 1995, Portland, USA, (** INVITED PAPER **).

244. R. Achar, R. Khazaka, R. Griffith, M. Nakhla and Q. Zhang, "Simulation of delay and crosstalk in VLSI interconnects", Proc. IEEE Canadian Electrical Engg. Conf, pp. 385-388, Sept. 95, Montreal, CA.

245. R. Achar, M. Nakhla and Q. J. Zhang, "Moment-matching techniques for transient analysis of high-speed VLSI interconnects with full-wave models", Proc. IEEE 25th European Microwave Conference, Sept. 1995, pp. 820-823, Bolongo, Italy.

Invited Talks/Tutorials (recent & selected)

1. "Scaling: Performance Challenges of High-Speed Interconnects”, Distinguished Lecture, DLP of IEEE EDS Society, Universitat Rovira, Virgili, Spain, Dec. 2021 (Virtual - Online).

2. "Scaling: Performance Challenges of High-Speed Interconnects”, Distinguished Lecture, DLP of IEEE EDS Society, Uttar Pradesh EDS Society, IIT Kanpur, Dec. 2021 (Virtual - Online)

3. "Scaling: Performance Challenges of High-Speed Interconnects”, Distinguished Lecture, DLP of IEEE EDS Society, IIT Roorkee Student Branch Chapter, IIT Roorkee, Dec. 2021 (Virtual - Online)

4. "Signal Integrity and High-Speed Designs", Distinguished Lecture, DLP of IEEE EDS Society, Cartagena, Colombia, Feb. 2019.

5. "Power Integrity Fundamentals and PSIJ Analysis", Invited Tutorial Presented in IEEE Intl. Conf. on Electrical Design of Advanced Packages (EDAPS-2018), Chandigarh, India, Dec. 2018.

6. "Signal Integrity and High-Speed Designs", Distinguished Lecture, DLP of IEEE EDS Society, IIT Roorkee, India, Dec. 2018.

7. "Signal Integrity and High-Speed Designs", Distinguished Lecture, DLP of IEEE EDS Society, Atlanta, GA, USA, Aug. 2018.

8. "Fundamentals and Advances in Power Integrity in High-Speed Low Power Designs", Invited Tutorial Presented in IEEE Intl. Symposium on Circuits and Systems (ISCAS-2018), Florence, Italy, May. 2018.

9. "Addressing High-Frequency Challenges in High-Speed Designs", R. V, College of Engineering, Bengaluru, Dec. 2017.

10. "Signal Integrity and High-Speed Designs", Distinguished Lecture, DLP of IEEE EDS Society, Lisbon, Porthugal, May 2017

11. "Signal Integrity and High-Speed Designs", Distinguished Lecture, DLP of IEEE EDS Society, Tarragona, Spain, May 2017

12. "Challenges and Opportunities: Modeling and Simulation for the Emerging High-Speed Multi-Function Designs, 11th International Conference on Scientific computing in Electrical Engineering, pp. 21-22, St. Wolfgang, Austria, Oct. 2016

13. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Singapore, July 2016.

14. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Bengalore, India, July 2016.

15. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Chennai, India, July 2016.

16. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Shanghai, China, May 2016.

17. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Nanjing, China, May 2016.

18. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Beijing, China, May 2016.

19. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Chengdu, China, May 2016.

20. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Hong Kong, May 2016.

21. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Split, Croatia, May 2016.

22. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Stellenbosch, South Africa, May 2016.

23. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Pretoria, South Africa, May 2016.

24. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Seoul, South Korea, Dec. 2015.

25. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Yokohoma, Japan, Dec. 2015.

26. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Sendai, Japan, Dec. 2015.

27. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Geelong, Australia, Dec. 2015.

28. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Melbourne, Australia, Dec. 2015.

29. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Ottawa Canada, Oct. 2015.

30. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Montreal, Canada, Aug. 2015.

31. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Manizales, Colombia, May 2015.

32. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Sao Paulo, Brazil, May 2015.

33. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Porto Allgre, Brazil, May 2015.

34. "Demystifying the Signal Integrity Challenges in High-Speed Designs", Distinguished Lecture, DLP of IEEE EMC Society, Buenos Aires, Argentina, Canada, May 2015.

35. Demystifying the Signal Integrity Challenges in High-Speed Designs", Invited Talk, University of Pune, India, Dec. 2014.

36. Demystifying the Signal Integrity Challenges in High-Speed Designs", Tutorial in IEEE Intl. Conf. on Electrical Design of Advanced Packages (EDAPS-2014), Bengaluru, India, Dec. 2014.Meeting the challenges of signal integrity issues in high-speed designs", IEEE Solid State Circuits Society, Noida, New Delhi and ST Microelectronics, Noida New Delhi, Jan 2014.

37. "Advanced Strategies for Power Integrity in High-Speed Low-Power Designs", Intel Penang, Malaysia, Dec. 2012.

38. "Meeting the challenges of signal integrity issues in high-speed designs", Workshop, Universiti of TAR, Malaysia, Dec. 2012.

39. "Meeting the challenges of signal integrity issues in high-speed designs", Nitte University, Nitte, India, Dec. 2012.

40. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of IEEE CAS Society, Beijing, China, Sept. 2012.

41. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of IEEE CAS Society, Singapore, Aug. 2012.

42. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of IEEE CAS Society, Montreal, Canada, July 2012.

43. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of IEEE CAS Society, St. Johns, Canada, July 2012.

44. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of IEEE CAS Society, Montevideo, Uruguay, May 2012.

45. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of IEEE CAS Society, Porto Allegre, Brazil, May 2012.

46. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of IEEE CAS Society, Santiago, Chile, May 2012.

47. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of CAS Society, Bangalore, India, Dec. 2011.

48. "High-Frequency Design Issues, Interconnects and Signal Integrity", Invited Guest Lecture delivered on the invitation of Ministry of Information Technology and Communications (MCIT) of Government of India (GoI) at the Super Computing Education and Research Center (SERC) of Indian Institute of Science (IISc), Bangalore, Dec. 2011.

49. "High-Frequency Design Issues, Interconnects and Signal Integrity", A three-day workshop conducted on the invitation of MCIT of Government of India at Indian Institute of Technology (IIT) - Kharagpur, India, Dec. 2011.

50. "High-Frequency Design Issues, Interconnects and Signal Integrity", A two-day workshop conducted on the invitation of MCIT of Government of India at Indian Institute of Technology (IIT) - Bombay, India, Dec. 2011.

51. "High-Frequency Design Issues, Interconnects and Signal Integrity", Invited Guest Lecture delivered on the invitation of MCIT of Government of India at Indian Institute of Technology (IIT) - Delhi, India, Dec. 2011.

52. "High-Frequency Design Issues, Interconnects and Signal Integrity", A two-day workshop conducted on the invitation of MCIT of Government of India at PSG Institutes of Technology (PSG-Tech), - Coimbatore, India, Dec. 2011.

53. "High-Frequency Design Issues, Interconnects and Signal Integrity", Invited Guest Lecture delivered on the invitation of MCIT of Government of India at Central Electronics Engineering Research Institute (CEERI), Pilani, India, Nov. 2011.

54. "High-Frequency Design Issues, Interconnects and Signal Integrity", Invited Guest Lecture delivered on the invitation of MCIT of Government of India at Birla Institute of Technology and Science (BITS), Pilani, India, Nov. 2011.

55. "Meeting the challenges of signal integrity issues in high-speed designs", Distinguished Lecture, DLP of CAS Society, Penang, Malaysia, Nov. 2011.

56. "Advances in signal integrity analysis techniques", Invited Talk, Asia-Pacific Design Automation TPC workshop, Taipei, Taiwan, Sept. 2011.

57. "Advanced modeling and simulation methodologies for signal integrity analysis", Invited Talk, Asia-Pacific Design Automation TPC workshop, Seoul, Korea, Sept. 2010.

58. "Parallel Algorithms for Power and Signal integrity Analysis in High-Speed Designs", Invited Talk, 42nd International symposium on Microelectronics - 2009, San Jose USA, Nov. 2009.

59. "Parallel EDA algorithms for the emerging power and signal integrity issues", Invited Talk, CMOS Emerging Technologies Workshop-2009, Vancouver, Canada, Sept. 2009.

60. "Fundamentals and Advances in signal and Power Integrity Analysis", Invited Talk, JSS College of Engineering, Bangalore University, Bangalore, India, Dec. 2008.

61. "Advanced Models for High-Speed Interconnect and Signal Integrity Analysis", Invited Talk, Microwave-2008: IEEE International Workshop on Recent Advances in Microwave Theory and Applications, Nov. 2008, Jaipur, India.

62. "Demystifying Microwave Signal Integrity: Fundamentals and Emerging Concepts in Signal Integrity Analysis", Invited Tutorial presented in IEEE International Microwave Symposium, June 2008, Atlanta, GA, USA.

63. "Advanced Modeling and Simulation Methodologies for Signal Integrity Analysis", Invited Talk, Distinguished Series Lecture of Academy of Taiwan Semiconductor Manufacturing Corporation, Taipei, Taiwan, Oct. 2008.

64. "Advanced Modeling and Simulation Methodologies for Signal Integrity Analysis", Invited Talk, Department of ECE, University of Illinois at Urbana-Champaign (UIUC), IL, Mar. 2008.

65. "Recent Advances in Modeling and Simulation of High-Speed Interconnects", Invited Talk, Electrical Design of Advanced Packaging and Systems Workshop (EDAPS), Taipei, Taiwan, Dec. 2007.

66. Fundamentals and Advances in Modeling/Simulation of High-Speed Interconnects for Signal Integrity Analysis", Invited Talk, First International Workshop on Interconnect Design and Variability (IDV), Bangalore, India, Dec. 2006. Also served as a panelist on design automation issues.

67. "Advances in Modeling and Simulation of High-Speed Interconnects for Signal Integrity Analysis", Invited Talk, EDAPS (Electrical Design of Advanced Packaging and Systems) workshop, Shanghai, China, Dec. 2006.

68. "Advances in Signal Integrity Methodologies", Invited Talk, presented in Signal Integrity Work-shop: I3WSI-2006, Guadalajara, Mexico, Oct. 2006.

69. "Disruptive Technologies for the next five years in Electronic Design Automation", Invited Talk, CANDE Meeting, Whistler, BC, Sept. 2006.

70. "Advances in Signal Integrity Methodologies and High-Speed Interconnect Analysis", Invited Talk, Cisco Systems, San Jose, July 2006.

71. "Advances in Signal Integrity Modeling", Invited Talk, Mentor Graphics, San Jose, Jun. 2005.

72. "Signal Integrity in High-Speed Designs", Invited Talk, Analog Devices, Boston, Mar. 2006.

73. "Signal Integrity in High-Speed Designs", Invited talk, ICFAI Institute of Science and Technology, Hyderabad, India, Jan. 2006.

74. "Signal Integrity in High-Speed Designs", 2 day workshop organized and presented, Bangalore, India, Dec. 2005. Also served as a panelist on signal integrity issues.

75. "Power and Signal Integrity", Short course/tutorial presented in Electrical Design of Advanced Packaging and Systems (EDAPS) workshop, Bangalore, India, Dec. 2005.

76. "Signal Integrity in High-Speed Designs", Invited Talk, Cisco Systems, San Jose, Nov. 2005.

77. "Advances in Signal Integrity Modeling", Invited Talk, Freescale Semiconductors, Austin, Oct. 2005.

78. "Signal Integrity in High-Speed Designs", Invited Talk, Texas Instruments, Dallas, Mar. 2005 (Delivered Online).

79. Fundamentals and Trends in Modeling and Simulation of High-Frequency/High-Speed Interconnects", Tutorial/Workshop to be presented in I3WSI-2005, Guadalajara, Mexico, Apr. 2005.

80. "Signal Integrity in high-speed designs", VLSI Society of India and Texas Instruments, Bangalore, India, Feb. 2005.

81. "Signal Integrity in VLSI designs - Modeling and Analysis", Broadcom, Bangalore, India, Feb. 2005.

82. "Signal Integrity in high-speed designs - Modeling and Analysis", Manipal Academy for Higher Education (MAHE), Manipal, India, Feb. 2005.

83. "Signal Integrity in high-speed designs - Modeling and Analysis", Birla Institute of Technology and Science, Pilani, India, Feb. 2005.

84. "Recent Advances in VLSI Design", Manipal Institute of Technology and IEEE Branch, Manipal, India, Feb. 2005.

85. "Signal Integrity in high-speed designs - Modeling and Analysis", Hangzou University, Hangzou, China, Jan. 2005.

86. "Signal Integrity: A Challenge in IC Design", Tutorial presented in 12th IEEE Mediterranean Electrotechnical Conference (MELECON-2004), Dubrovnik, Croatia, May 2004.

87. "Trends and fundamentals in Modeling and Simulation of High-Speed Interconnects", Tutorial/ Workshop presented in IEEE International Microwave Symposium, Fort Worth, Texas, June 2004.

88. "Modeling of High-Frequency Subnetworks", Gennum Corporation, Ottawa (talk was also attended by designers from Gennum, Burlington through teleconferencing), Sept. 2003.

89. "Connector Modeling", Gennum Corporation, Ottawa (talk was also attended by designers from Gennum, Burlington through teleconferencing), Mar. 2003.

90. "Signal Integrity analysis in High-Frequency circuits", Cadence Design Automation Systems, Chelmsford, MA, USA, September 2002.

91. "Recent progress in Simulation/Modeling of high-Speed interconnects", tutorial presented in 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, Dubrovnik, Croatia, 2002.

92. "Multi-level model-reduction approaches for high-speed interconnect simulation", Gennum Corporation, Ottawa (talk was also attended by designers from Gennum, Burlington through teleconferencing), Mar. 2002.

93. "Recent progress in simulation and modeling of high-speed interconnects", tutorial presented in IEEE International Workshop on Signal Propagation on Interconnects, Venice, Italy, May 2001.

94. "Model-reduction techniques for high-speed interconnect analysis", Invited talk presented in Journées Nationales des Micro-ondes [J.N.M.], Poitier, France, May 2001.

95. "Managing Complexity of High-Speed Systems through Model-Order Reduction", IBM Advanced Packaging group (Poughskpee), New York, August 2000.

96. "Managing high-speed design complexities through model-reduction tools", Gennum Corporation, Toronto, Ont., Dec. 99.

97. “Simulation and modeling of high-speed systems”, Workshop on Manufacturing and Packaging, Ottawa, Ont., Apr 99.

Contact

Professor Ram Achar

Department of Electronics, Carleton University
Ottawa, Ontario, Canada - K1S 5B6
Ph: 613-520-2600, Ext: 5651; Fax: 613-520-5708
Email: achar@doe.carleton.ca

URL: http://www.doe.carleton.ca/~achar

Other Useful Links

Department of Electronics

Carleton University

Graduate Studies @ Carleton

International Students Information

OCIECE: Ottawa-Carleton Institute for Electrical and Computer Engineering (for online graduate studies applications)

Computer-Aided Engineering Research Lab

4th Year Projects

Projects:

Development of High-Speed Interconnect Models and Efficient Simulators
Numerical Algorithms for Circuit Simulation
Sensitivity Analysis and Optimization
Mixed-Domain Simulation
Signal Integrity Analysis Methodologies

Introduction: With the continually rising operating frequencies, interconnects are becoming major bottlenecks for high-speed designs. High-speed interconnect effects such as ringing, signal delay, distortion, reflections and crosstalk can severely degrade the system performance. Interconnects can exist at various levels of design hierarchy such as on-chip, packaging structures, multichip modules, printed circuit boards and backplanes. However, conventional circuit simulators do not handle the interconnect analysis efficiently.

Goal: The objectives of this project are:

To develop interconnect models that are suitable for inclusion in SPICE-like conventional simulators.
To develop efficient simulation algorithms and software tools for high-speed circuit analysis.

Requirements:

· Strong background in mathematics (specifically in linear systems, ordinary differential equations, Laplace transform, Numerical analysis),

· Good proficiency in software development and programming (C or C++ or Java and Matlab).

· Strong analytical ability

Each participating student will be assigned a specific module of the project.

Financial Aid, Graduate Student Opportunities

· Several research positions (RA) and at post-doctoral/Ph.D./masters levels are currently available in my research group. Research projects are directed toward advancing the state-of-the-art in computer-aided design methodologies and tools for mixed-domain and high-frequency VLSI circuits and systems.

· The intake to the group is highly competitive. Only those students who consistently excelled in their academic performance and with strong analytical skills are encouraged to apply.

· Summer positions for undergraduate students are available. Interested students (with strong academic performance) are encouraged to contact well in advance (preferably two-terms) for such positions.

· The interested candidates may also want to explore the following additional funding opportunities through various agencies:

Postdoctoral Fellowship Opportunities

Canada Scholarships

NSERC Postdoctoral Programs

Commonwealth Scholarships

MITACS Fellowships

Info from Government of Canada Site

Banting Postdoctoral Fellowships

Info on Other Scholarships

Graduate Student Opportunities

NSERC Postgraduate Programs

Vanier Canada Graduate Scholarships

Info from Government of Canada Site

Info on Other Scholarships

Undergraduate Student Opportunities

NSERC Undergraduate Student Research Awards

Info from Government of Canada Site