5401 Fall 2012, (Graduate Course)


Signal Integrity in High-Speed Designs: Modeling and Analysis



Ram Achar (DOE, Carleton)

Email: achar @ doe.carleton.ca




The rapid growth in VLSI circuit technology coupled with the trend towards complex/miniature devices is placing enormous demands on computer-aided design (CAD) tools focused on microelectronics. The design requirements are becoming very stringent, demanding higher operating speeds, sharper excitations, denser layouts and low power consumption. Consequently, signal integrity issues such as delay, attenuation, crosstalk, ground bounce etc. are becoming major bottlenecks in design and validation of high-speed circuits and systems.


High-speed effects, if not addressed properly during the design stage, can cause logic glitches which render a fabricated digital circuit inoperable, or they can distort an analog signal such that it fails to meet specifications. Since extra iterations in the VLSI design cycle are extremely costly, accurate prediction of these effects is a necessity in high-speed designs. A paradigm shift is currently taking place in both the design and CAD community to adapt to the new requirements of high-speed design issues. However, currently available CAD tools and design strategies do not handle the complex scenario of high-speed circuit design/analysis encompassing diverse domains, adequately.


This course would focus on understanding high-speed signal integrity issues, developing new generation CAD tools to model and analyze these effects, and also on developing design strategies to handle them. Following is a broad outline of the materials proposed to be covered in this course:



         Introduction and motivation, Signal propagation in interconnects, High-speed design and signal integrity issues: Delay, Crosstalk, Attenuation, Ringing and Reflections, Switching Noise, Eye Diagrams, Case Studies.


         Brief Review of Computer-aided Design for Circuit Analysis: Modified Nodal Analysis, Frequency Domain Analysis, Transient Analysis.


         Modeling of High-speed Interconnects/Packages: Elmore Delay, RC Trees, RLC Lumped Interconnect Models, T, Pi Structures, Coupled, Lossless and Lossy Lines, On-Chip Interconnects, Power/Ground Planes, Power Distribution Issues and power integrity, Inductance Effects, Ground Bounce Analysis, Packaging Structures, Issues.