IC Streams: Custom Integrated Circuits Design bundle
 -VirtuosoR Analog Design Environment
 -VirtuosoR AMS Designer Environment
 -CadenceR SKILL Development Environment
 -VirtuosoR Schematic VHDL Interface
 -VirtuosoR Schematic Editor VerilogR Interface
 -VirtuosoR Schematic Editor XL
 -VirtuosoR Analog Oasis Run-Time Option
 -VirtuosoR Layout Suite
 -DivaR Physical Verification and Extractor
 -VirtuosoR Schematic Editor HSPICE
 -VirtuosoR Schematic Editor SpectreR
 -VirtuosoR Analog Design Environment
 -VirtuosoR Analog HSPICE Interface
 -VirtuosoR Layout Suite
 MMSIM Bundle: Analog circuit Simulator
 -VirtuosoR UltraSim Full-chip Simulator
 -VirtuosoR SpectreR Analog Circuit Simulator
 -VirtuosoR SpectreR RF Simulation
 Assura Bundle: Design Rule Checker bundle
 -Layout vs. Schematic Verifier
 -Parasitic Extractor
 -RCX Field Solver
 -RCX Parasitic Inductance
 -RCX and TM  Multiprocessor
 -RF Bundle
 SPB Streams: PCB Design
 -Cadence SiP Digital Architect
 -Cadence SiP Digital SI
 -Cadence SiP Digital Layout
 -AllegroR PCB Librarian, HDL and CIS Design
 -AllegroR PCB SI
 -AllegroR Package Designer and SI 
 -AllegroR Orcad Family
 ANLS Bundle: Analyser
 -CeltIC NDC Crosstalk Analyzer with Delay Calculator
 -SignalStorm NDC Nanometer Delay Calculator
 -SignalStorm Library Characterizer
 SOC Bundle:System on a Chip Virtual Prototyping
 -SOC Encounter Global Physical Synthesis 
 -Route Accelerator Multi-Threaded Route
 ET Bundle: Testing
 -EncounterR Test Architect
 -EncounterR True Time Test
 -EncounterR Diagnostics
 IUS Bundle: Design & Verification
 -VirtuosoR AMS Designer Simulator
 -Functional Simulation (NC-Sim, NC-Verilog, NC-VHDL and Verifault-XL simulators
 -TestBuilder is a C++ class library for HDL and Verilog verifications
 -FormalCheck model checking tool