April 25, Question
Response
April 25, Question We are looking a setting the gate voltages in the Folded Cascode and were wondering if/when do we use Von = Von + Safety or simply Von?
Do you ever use Safety anywhere else?
Response Von is the minimum VDS to keep a transistor operating in the saturation region. Anything less and it is in the triode region and current is no longer constant, and output impedance of the transistor goes down. For this reason, you typically don't want to operate right on the edge, so you would always operate nominally with a VDS slightly bigger than the minimum possible. So your question of where do you use safety is essentially whenever you do design, you choose a Vds slightly bigger than the minimum. You might not always call it Safety, but it is usually there.
So when do you not use it? Whenever you are determining the border between saturation and triode. An example would be when you are calculating the voltage extreme, such as for common-mode input range or output voltage range. In such a case you might do a calculation where the limit of useful operation would be at some point where Vds=Von.
Note your statement that Von=Von+Safety is not correct. The correct statement is Vds=Von+safety.
April 25, Question In your 2000 midterm solution, number 3, is the slope shown correctly?
Response Oops! The slope should be 53V/usec, or 5.3V/100ns. What I have shown is not 5.3V, but about half that (from +0.5 to about -2). So the slope should have been about twice as steep.
April 24, Question In doing a charge balance, how do I pick whether "time now" is on phase 2 or phase 1?
Response Either way, you can solve the problem. However, I would tend to pick the time where most of the charge transfer happens.
Note the following cases do not involve charge balance involving an opamp or a voltage source charging a capacitor to ground
Charge balance is done when two (or more) capacitors are connected together, and charge is transferred between them. Such a connection is most often at the input of an opamp.
April 24, Question I noticed that at "time now" you have an input listed as "V2,n-1/2". If it is time now, why is it at n-1/2? Shouldn't it be "V2,n"?
Response The point you are talking about is on the sample and hold capacitor which has sampled the input half a clock cycle ago. So even though it is "time now", the voltage is what was sampled earlier. Maybe it would help if we labeled that node as Vx. Then Vx,n=V2,n-1/2. However, we don't really want an extra variable, so we just label it with V2,n-1/2.
April 24, Question Can you put up the midterm and solutions on the web page?
Response I will try to do so later today, Monday April 24. Comment later at 9:00 PM Monday April 24. The midterms and solutions are now up on the web page
April 24, Question I am working on the sample exam from last year. I am not sure how to answer question 5 and the question is: what is the techniques for cmos op amp design to achieve stability in closed loop.
Response The following points would be useful.
In general, for a two pole system, make sure second (parasitic) pole occurs at a frequency higher than unity gain bandwidth. If more poles, or zeros are involved, (such as for pole splitting opamps), may need their frequencies somewhat higher than unity gain frequency.
Know what determines dominant and parasitic poles and unity gain bandwidth. For example in the folded cascode, w_u = gm1/CL. Parasitic pole occurs at the summing node out of the differential pair which is where M2, M5 and M7 join. So can adjust sizes etc to set RC time constant at this node, where R=1/gm7, C is sum of capacitances of due to M2, M5, and M7.
Typically use simulation of magnitude and phase to determine stability by checking the phase (and phase margin) at the unity gain frequency. The above calculations are a starting point and can help to see how to adjust a circuit to make it more stable. For example to increase stability:
The above, if written up properly is already more that you need to get full marks. At the time this question was written, the pole-splitting amplifier was being studied, so discussion of the affect of zeros in the right-half plane were expected. This year, such discussion would not be expected.
April 24, Question I've encountered a question on op-amp stability. What is the relationship of op-amp stability to system performance in SC circuits, and how stability can be achieved?
Response If an opamp is completely unstable, then obviously a switched-capacitor filter won't work. If the stability is marginal, that is low phase margin, then there would be ringing on steps which would affect settling which would directly affect switched capacitor filters. To operate under such conditions, one would have to reduce the clock rate to allow complete settling.
April 21, Question I tried the 97 exam and got hung up all over the place.
Response I did both of these exams in the last few days of class, so information is available in your class notes. I discussed in a fair bit of detail some of the types of things students might have trouble with, so, most things were covered. However, I can give a little more detail here as well.
April 20, Question You have probably answered this question already but I cant seem to get the correct answer and was hoping you could show me the way to do it (it's frustrating, because I thought I understood this).
Exam April/99. question 1d) common mode range
Response Exam 99, 1d. Common Mode Range. The thing to remember is:
For NMOS: Vds >= Vgs-Vt or Vd-Vs >= Vg-Vs-Vt or Vd>=Vg-Vt
Thus, drain voltage can be lower than gate voltage by up to a Vt. Similarly, for PMOS, drain voltage can be higher than gate voltage by |Vt|.
Negative Range
Vx is fixed at 1.5V for good amplifier operation. This is Vd of a PMOS transistor M2, thus this voltage can be up to a |Vt| higher than the gate voltage which is also the common-mode input voltage vc. Thus vc can go down to 1v.
Positive Range
M3 will eventually go out of saturation as its drain voltage Vz goes too high. Vz can up to bias voltage plus |Vt| or up to 4V. Then for this voltage if you know the VGS of M1 and M2, you can calculate the input voltage. Note, since there is constant current, there is constant Vgs across M1 and M2. M1 and M2 each have 100 uA of current, are 18/1 and have Kpp of 25 uA/V^2 so VGS can be calculated from 100u=25u/2*18*(Vgs-Vt)^2 or solving for Vgs=sqrt{2*100u/(18*25u)}+Vt = 2/3+0.5=1.1667. Then Vc=4-1.1667=2.8333V
April 20, Question In question 5d) your solutions use a transfer function for a non inverting amp(1+zf/zi) ? why, if before it was inverting
Response Noise due to the opamp itself is referred to one of its input terminal, and the positive intput terminal isn't being used so it is a convenient place to put it. Previously we were calculating noise from components whose transfer function was inverting.
April 20, Question You ask for the noise density isn't that the input noise multiplied by the square of the transfer function (spectral noise density), your solution doesn't appear to do this ?
Response Noise density quite often means power spectral density, but in opamps it is quite common to specify voltage density as in 7 nV/sqrt{Hz}. These two are simply related by square or square root. Where it is important is when you are combining different noise sources, or noise at different frequencies, then you must sum power and not voltage. Thus integrals to find total integrated output noise always uses PSD multiplied by square of the magnitude of the transfer function. As a result you get volt squared as an answer, but you can always convert back to voltage by taking a square root.